Project kickoff and quick context

• Tell me about the product and prototype that pushed the BOM decision onto your radar right now
• How many weeks remain until your formal BOM lock or design freeze? Options: Under 4 weeks, 4 to 8 weeks, 9 to 16 weeks, More than 16 weeks
• Who on your team will be the primary technical contact for component evaluations and FAE sessions? Options: Hardware lead/engineer, Firmware/embedded engineer, Engineering manager, Program manager, Other
• Which parts of the prototype are most constrained by package, power budget, thermal headroom, or cost? Options: Processor/microcontroller area, Power regulation area, RF/connectivity section, Sensor cluster, Mechanical/space-constrained area, Other
• Estimate the minimum number of sample units you would need per candidate to complete board bring-up and parallel testing, or explain if you are flexible Options: 1–2 units, 3–5 units, 6–10 units, More than 10, Flexible, explain in next field

Reality check: where the current setup breaks down

• When an allocated or single-sourced component shows up in a prototype BOM, how does that usually affect your delivery calendar?
• Describe the last time a prototype required rework because the chosen component failed to meet a board-level constraint, and who owned the fix
• How often do you hit unexpected power sequencing, thermal, or signal-integrity problems during initial bring-up? Options: Almost every prototype, Often, Occasionally, Rarely
• Walk me through your current board bring-up workflow, from sample arrival to a validated test case
• If your current prototype part remains unavailable for another 40 weeks, what single project outcome would you consider a showstopper? Options: Delay to product launch, Feature cut to meet schedule, Switch to different architecture, Cancel project, Other

Hard trade-offs and non-negotiables

• Rank these trade-offs in order of what your team refuses to compromise on: power consumption, package size, throughput/performance, unit cost Options: 1=Top priority, 4=Lowest priority
• Tell me how you weigh second-source availability against per-unit pricing when deciding which silicon to evaluate first Options: Balanced case-by-case, Second source trumps price, Price matters more early, second source later, No formal weighting
• Identify the role that must sign off on a vendor design registration or locked pricing for this project Options: VP/Head of Engineering, Program/Product Manager, Procurement/Buyer, Operations/Production, Other
• Typically, how many weeks of lab validation do you budget before a design is considered locked for procurement planning? Options: Under 2 weeks, 2–4 weeks, 5–8 weeks, More than 8 weeks
• List any hard constraints that would make a candidate part unusable even if it otherwise met specs, for example unacceptable package type, missing peripheral, or unsupported voltage rail Options: QFN incompatible with assembly, No required ADC or DMA, Package too large for enclosure, No second-source available, Other

Where the process trips you up

• Why do past component choices create late surprises or require rework in your experience?
• Recall a recent allocation, lead-time, or sample shortage incident and summarize the mitigation steps you took
• Estimate how often sample shortages or late shipments have forced you to change a test plan or delay a milestone in the last year Options: Never, Once, 2–3 times, 4+ times
• Name the internal stakeholder who most often blocks or slows sample orders because of procurement or compliance constraints Options: Procurement/Buyer, Vendor management, Security/Compliance, Program manager, Other
• Would a guaranteed sample shipment within your prototype window be the difference between proceeding with an evaluation or pausing it? Options: Yes, we would proceed immediately, Maybe, depends on other factors, No, other constraints would still block us

Competitive landscape, who else could you do this with?

• List the alternatives you are actively evaluating or have already considered, including direct manufacturer channels, other distributors, or an internal sourcing plan Options: Direct manufacturer, Other technical distributor, Broadline distributor, Internal sourcing, No alternatives evaluated
• Under what conditions would you stay with your incumbent component instead of switching to a different candidate? Options: If pricing stays stable, If second source appears, If performance is unchanged, If timeline impact is negligible, Other
• Do you have an internal proposal to solve sampling or evaluation without outside FAE support, and if so describe the core of that plan Options: Yes, internal lab can handle, Partially, need limited outside help, No, we rely on external FAEs
• Does any alternative you're considering include dedicated FAE hours, reference design adaptation, or guaranteed kit provisioning? Options: Yes, full FAE support included, Some support but limited hours, No FAE support offered, Unclear from current alternatives
• What would have to be true about a competitor or internal approach for you to prefer it over using an external distributor with embedded FAEs? Options: Lower total cost, Faster sample availability, More comprehensive FAE time, Better roadmap access, Other

How you plan to validate candidates in the lab

• Imagine you have two weeks of bench time, which validation must succeed in that window to keep the project on schedule: power profile, boot reliability, throughput, or thermal margin? Options: Power profile, Boot reliability, Throughput/latency, Thermal margin, All of the above
• Point to the evaluation kits, reference designs, or measurement setups you already have that we could reuse for faster validation Options: Manufacturer eval kits, In-house breakout boards, Custom reference PCB, No reusable kits available, Other
• Specify the minimum sample quantity and any special test accessories you need for parallel board-level comparison Options: 1–2 per candidate, 3–5 per candidate, 6–10 per candidate, Test accessories required (e.g., power harness)
• Do you require on-site bench sessions, remote debug with screen share, or a combination for the FAE-led bring-up? Options: On-site bench time, Remote debug sessions, Combination of both, No preference
• Which internal approval or sign-off will immediately allow ordering production-qualifying samples if a candidate meets acceptance criteria in the lab? Options: Engineering sign-off, Program manager approval, Procurement release, Operations/production readiness

Operational readiness and practical constraints

• Identify third-party systems, APIs, or lab infrastructure that must be available before an FAE can validate your board in-circuit Options: Power supplies and load boards, Telemetry/measurement systems, Firmware toolchains and JTAG access, Networked test racks, No external dependencies
• Provide the names of roles who will own sample receipt, inventory, and disposition during the evaluation Options: Hardware engineer, Lab manager, Procurement, Program manager, Other
• Are there compliance, security, or procurement approvals that typically delay sample acceptance at your facilities? Options: Yes, security screening, Yes, procurement paperwork, Yes, import/customs constraints, No major approvals required
• State any assembly, carrier board, or mechanical constraints that would prevent you from testing a candidate on your reference PCB Options: Different package pitch, Special power rails, Thermal interface needed, No constraints
• If you cannot provide JTAG or firmware access for an initial test, would that stop the evaluation or can the seller's FAE proceed with black-box testing? Options: Stop evaluation until access provided, Proceed with black-box tests, Depends on the candidate and test objectives

Success signals and the path to a mutual commit

• Point to the single metric or acceptance test that, if achieved, would make you ready to commit to a design registration or sample order Options: Power under target, Boot reliability across samples, Throughput/latency target, Pass thermal margin
• Rank these procurement concerns in order of urgency for production readiness: pricing stability, lead time, second-source availability, lifecycle roadmaps Options: 1=Most urgent, 4=Least urgent
• Explain the internal timeline from successful evaluation to when procurement must see a held price or lead-time commitment
• When would you be prepared to run a funded pilot or register a design if a candidate meets the agreed acceptance criteria? Options: Immediately, Within 2 weeks, Within 1 month, Longer than 1 month
• Would a shared channel for ongoing issues and a named FAE for follow-up make you more likely to move from evaluation to design registration quickly? Options: Yes, Maybe, No

• Solution Walkthrough & Lab Plan

• Confirm the current state and its cost to your team
• You confirm the stated current-state description and the quantified schedule and rework cost.
• Deliver an itemized evaluation kit and sample list mapped to each acceptance criterion, including recommended sample quantities and estimated lead times within three business days.
• You confirm the acceptance criteria and agree that the proposed lab tests will prove compliance against your real circuits.
• Align acceptance criteria to measurable tests
• Produce a draft lab test procedure that maps each test step to the pass/fail thresholds agreed in the session.
• Provide the latest prototype schematic, BOM, and one representative test case for the planned validation within three business days.
• You agree to the sample quantities, FAE support window, and timeline required to produce test evidence for design registration.
• Walk your prototype integration points
• Schedule the hands-on bench session and confirm attendees and the preferred test window.
• You identify any remaining gaps in the plan that must be closed before ordering samples or committing to registration.
• Show the lab validation plan and roles
• Surface failure modes and contingencies
• Agree the go/no-go sign-off criteria and the checkpoint for design-registration next steps after validation.
• Forced validation, confirm this matches your need

• Solution Walkthrough & Lab Plan
• Solution Walkthrough & Lab Plan Deck
• Solution Brief — Solution Walkthrough & Lab Plan

• meeting
• slides
• document

• Provision Evaluation Kits and Sample Parts
• Deliver Board-Level Reference Design Package
• Adapt Reference Design to Buyer Schematic
• Review and Annotate Schematic with Corrections
• Assemble Prototype Evaluation Boards
• Debug Power Sequencing on Prototype Hardware
• Provide Application Firmware Examples and Drivers
• Measure Power Consumption and Thermal Profile
• Supply PCB Footprint and Land-Pattern Files
• Integrate and Test Sensor or Connectivity Module
• Deliver BOM with Second-Source Component Options
• Provide Reference PCB Layout and Stack-Up Guidance
• Run High-Speed Signal-Integrity Fixes on Prototype

Provision Evaluation Kits and Sample Parts

• Do you require full evaluation kits or single-part samples for first-pass testing? Options: Full evaluation kit, Single-part samples, Both
• How many sample parts do you need per candidate device for parallel validation on your benches? Options: 1-3, 4-10, 11-50, 50+
• Which shipping conditions matter for your receiving site (standard ground, temperature control, hazardous materials, expedited)? Options: Standard ground, Temperature-controlled, Hazmat/regulated, Expedited air
• Provide the target project milestones tied to sample delivery (for example: first bench test on day 14, design review on week 6)
• Identify any import, export, or internal procurement approvals required by your receiving operations team

Deliver Board-Level Reference Design Package

• Which file types do you need in the reference package (Gerber, source CAD, BOM CSV, assembly drawings, pick-and-place)? Options: Gerber, PCB CAD (source), BOM CSV, Assembly drawings, Pick-and-place, 3D STEP
• Provide the functional tests and pass/fail criteria that the reference board must demonstrate for your design-in acceptance (for example: boot to application, ADC SNR threshold, peripheral init within X ms)
• List any footprint or library standards your PCB team requires (for example IPC-7351, manufacturer footprint ID, internal library reference)
• Specify whether you need fabrication-ready Gerbers or source CAD files for internal modifications Options: Fabrication Gerbers, Source CAD files, Both

Adapt Reference Design to Buyer Schematic

• Describe the schematic differences we should adapt for (net names, power-rail mapping, alternate connectors, mechanical connectors)
• Identify the pin mappings or alternate footprints in your schematic that require cross-wiring changes on the reference board
• Indicate the target mechanical constraints to respect during adaptation (board dimensions, keepouts, connector locations in millimeters)
• Specify the acceptable number of board revision cycles included for adaptation Options: 1, 2, 3, More than 3 (requires change order)
• Confirm who on your team will approve the adapted schematic and PCB drawings

Review and Annotate Schematic with Corrections

• List the schematic documents we should review (for example PDF schematic, native CAD file, netlist)
• Name the critical nets or power rails that need focused annotation (for example VDD_CORE, VDDA, VBAT)
• Describe the level of annotation required (component-value checks, decoupling verification, signal-integrity notes)
• Choose the expected turnaround time for annotated schematic review Options: 48 hours, 5 business days, 2 weeks, Custom
• Confirm the format you want annotated deliverables returned in (PDF with comments, annotated CAD file, markup spreadsheet) Options: PDF with comments, Annotated CAD file, Markup spreadsheet

Assemble Prototype Evaluation Boards

• Do you require hand-assembled prototypes or a small factory-assembled run? Options: Hand-assembled (bench), Small factory run, Either
• How many prototype boards do you need for lab validation and integration testing? Options: 1-3, 4-10, 11-25, 26+
• Indicate the acceptable component substitutions or second-source rules for assembly (value tolerances, case sizes, approved alternates)
• State stencils, solder paste, or SMD assembly preferences (for example type 3 paste, no-clean flux, stencil aperture notes)
• Name any test jigs or fixtures required for board acceptance

Debug Power Sequencing on Prototype Hardware

• State the power rails and sequencing order your design requires (for example VDDIO before VDD_CORE, POR thresholds in volts)
• Explain the symptoms you've observed or the failure modes to reproduce during debugging (brownout, reset loops, dead boot)
• Share the bench equipment available to you for debugging (oscilloscope bandwidth, power supply with sequencing, logic analyzer, current probe) Options: Oscilloscope with probes, Power supply with sequencing, Logic analyzer, Current probe, All of the above
• Estimate how many FAE support hours you expect for power-sequence debugging Options: 1-4 hours, 1 day, 2-3 days, More than 3 days
• Outline the test procedure you use to reproduce the sequencing issue on your bench (step-by-step, input voltages, connectors)

Provide Application Firmware Examples and Drivers

• Tell us the MCU SDK or real-time operating system (RTOS) you use or prefer in your prototype (bare-metal, FreeRTOS, Zephyr, other) Options: Bare-metal, FreeRTOS, Zephyr, Other
• Share the peripheral use-cases your firmware must demonstrate (for example ADC sampling at X ksps, UART bootloader, I2C sensor read)
• Select the language and toolchain required for examples and drivers (C, C++, ARM GCC, IAR, Keil) Options: C, C++, ARM GCC, IAR, Other
• Are there security or code-signing requirements for delivered binaries? Options: Yes, No
• Choose whether example drivers must be provided as source code with build scripts or binaries only Options: Source code with build scripts, Binary examples only, Both

Measure Power Consumption and Thermal Profile

• Select the operating modes to be profiled (for example active, sleep, low-power idle, deep sleep) Options: Active, Sleep, Idle, Deep sleep
• Write the exact test load conditions for power measurements (clock frequency, enabled peripherals, sample workload in mW or MIPS)
• Give the thermal environments and ambient temperatures for thermal profiling (for example 25°C, 60°C, enclosure closed)
• Tell us the instrumentation you expect us to use for measurements (DC current probe, source-measure unit, thermal camera, data logger) Options: DC current probe, Source-measure unit (SMU), Thermal camera, Data-logger
• Give the maximum allowable active and standby currents (in mA/µA) that will define acceptance for your design-in

Supply PCB Footprint and Land-Pattern Files

• Supply the preferred footprint standards your PCB CAD team requires (for example IPC-7351, manufacturer drawing, internal library ID)
• Enumerate the package variants you need footprints for (QFN, LGA, BGA, TQFP) and indicate pin counts where applicable
• Enumerate the file formats required for CAD import (for example IPC-2581, ODB++, Altium PCBLIB, KiCad) Options: IPC-2581, ODB++, Altium PCBLIB, KiCad, Other
• Write your solder mask expansion and courtyard clearance preferences in mils or millimeters
• Attach any solder paste stencil aperture guidelines or paste-threshold rules you require

Integrate and Test Sensor or Connectivity Module

• Declare the sensor or module interfaces that must be validated on your board (for example I2C, SPI, UART, SDIO, USB) Options: I2C, SPI, UART, SDIO, USB, Other
• Detail the data-rate and throughput targets for the connectivity module under expected loads (specify in kb/s or Mbps)
• Outline the environmental tests required for the sensor (temperature range, humidity, shock) with numeric thresholds
• Define the functional acceptance criteria for the sensor or module (for example accuracy ±X units, false-positive rate, packet error rate)
• Detail any antenna or RF layout constraints to preserve link performance (keepout area, board edge clearance in millimeters)

Deliver BOM with Second-Source Component Options

• Declare the critical long-lead or single-source components that require second-source alternatives
• Sketch acceptable substitution rules for passive components (value tolerance, case size, temperature coefficient)
• Mark the price-band or target unit-cost thresholds you want the BOM to reflect Options: <$0.10, $0.10-$1, $1-$10, $10+
• For procurement, list your preferred distributors or procurement channels for sourcing comparisons
• Explain the qualification testing required for identified second-source components

Provide Reference PCB Layout and Stack-Up Guidance

• For stack-up, provide number of layers, dielectric thickness, and core materials in your target manufacturing units
• For high-speed routing, specify constraints to follow (impedance control, differential pair spacing, maximum trace length)
• For EMI, list the board-level mitigation requirements you need (filter placements, common-mode chokes, ground pours)
• For layer assignments, indicate preferred assignments for power, signals, and ground
• For DRC, specify whether you require rule files for your board house and which CAD tool format Options: Altium rules, IPC DRC, Custom DRC file, None

Run High-Speed Signal-Integrity Fixes on Prototype

• For high-speed nets, name the interfaces that need SI fixes (for example USB3, PCIe, DDR routing, LVDS)

• Design Registration Agreement
• Sample Order & Authorization
• Pricing & Lead-Time Commitment
• Statement of Work (SOW) — Evaluation & FAE Support
• Master Services Agreement (MSA) for FAE Services
• Acceptance & Escalation Protocol

• Go-live health check (weeks 1-4)
• First measurement review (weeks 4-10)
• Acceptance gate review (around day 90)
• Ongoing quarterly success review

• Publish a short status summary in the shared channel ahead of the next quarterly meeting, including any production risks.
• Produce a documented per-criterion pass/fail record against the Solution Scope targets.
• Capture the buyer's documented go or no-go decision on the evaluated components and next immediate steps.
• If required, record a remediation plan with concrete milestones and a verification date.
• Publish the acceptance results document showing pass/fail per criterion and the buyer's documented decision.
• Create and circulate a remediation plan for any failed criteria with milestones and verification dates.
• If accepted, update the production-readiness tracker with confirmed lead times and preliminary pricing commitments.
• Production-readiness signals
• Confirm production-readiness metrics, including current lead time and verified unit pricing at target volume, are tracked and within acceptable bounds.
• Ensure all open issues are assigned resolution dates and that second-source qualification progress is visible and on track.
• Maintain an agreed shared channel and escalation workflow for production or field issues.
• Update the lead-time and pricing tracker monthly and circulate the updated sheet before the next quarterly review.
• Document the current second-source qualification status and list remaining steps to qualify alternate suppliers.
• Re-confirm acceptance criteria and owners
• Confirm prototypes are operational and basic functional checks have passed.
• Document all open blockers with clear remediation tasks and due dates.
• Confirm schedule and data sources for the first measurement meeting.
• Publish current prototype build status and a list of device serials used in evaluation.
• Document firmware and schematic review notes and circulate to stakeholders.
• Schedule the first measurement data collection window and specify the test procedures to be used.
• Present first-data snapshot against Solution Scope targets
• Determine whether prototype pass rate and power consumption are trending to the Solution Scope targets and identify any gaps.
• Agree concrete remediation tasks and dates required to meet acceptance criteria at the day-90 gate.
• Capture current sample counts, unit pricing indicators, and lead-time observations for production-readiness tracking.
• Run the agreed focused bench tests to isolate observed failure modes and publish results in the shared channel.
• Order additional prototype samples or evaluation kits if test coverage is insufficient for acceptance decision.
• Update the sample and lead-time tracker with current vendor lead-time estimates and tentative pricing.
• Restate acceptance criteria and numeric targets
• Deployment and bring-up validation
• Present outcome data against each criterion
• Open issues and enhancement request burn-down
• Root-cause diagnosis for any metric gaps
• Shared support channel and escalation process check
• Sample availability and preliminary supply signals
• Early adoption and support signals
• Document pass/fail per criterion and buyer decision
• Agree corrective actions and timeline to acceptance gate
• Agree remediation plan and resolution timeline for any failed criteria
• Quarter plan and data cadence
• Open issues and blockers
• Agree immediate remediation actions and timeline