Opening the Technical Conversation

• Tell me briefly which vehicle platform program is driving your move to a zonal Ethernet backbone and the platform freeze date you are working toward
• How many ECUs or separate domains do you expect to migrate to the zonal backbone in your first production wave Options: 1-10, 11-50, 51-200, 200+
• What are your top three measurable priorities from this list, rank them if possible Options: Data rate, Deterministic latency, EMC margin, Sleep-mode power, AUTOSAR compliance, OPEN Alliance compliance, Diagnostic visibility
• Describe the people and roles that must sign off on silicon selection and network architecture at your organization

Where the current network falls short

• Which single risk in your current approach would make you stop the program immediately if it could not be mitigated Options: EMC failure, Latency out of spec, Sleep power too high, Protocol incompatibility, Supply continuity, Other
• When interoperability problems have occurred on past projects, what happened and what was the downstream impact on schedule, cost, or warranty
• Who on your team typically detects protocol or EMC incompatibility first, and what is the escalation path from discovery to resolution Options: Hardware validation lead, System architect, Software integration lead, EMC lab contact, Tier 1 integration team, Other
• How do you currently validate EMC on early evaluation boards and how often have boards required rework because of EMC issues Options: Pre-compliance lab, Full automotive EMC lab, Supplier reports only, In-vehicle testing only, No formal EMC tests yet

Performance priorities and trade-offs

• If you had to sacrifice one performance attribute to meet timeline or power constraints, which would you accept and why Options: Data rate, Latency, EMC margin, Sleep-mode power, Diagnostics detail, Other
• In your benchmarking so far, what latency and jitter targets have proven hardest to hit and on which topologies or evaluation-board scenarios
• Which evaluation-board test cases cause the most integration rework in your experience Options: EMC radiated immunity, EMC conducted emissions, Sleep-mode power under wake scenarios, Gateway bridging message bursts, AUTOSAR/OPEN Alliance compliance tests, Other
• Could failing to meet sleep-mode power targets force feature cuts or block OEM approval for the vehicle program Options: Yes, approval would be blocked, Yes, would force feature cuts, Would require additional mitigation but not block, No major impact, Unsure

Timeline pressure and decision gates

• Why is your platform freeze date nonnegotiable and what happens to the program if silicon is not qualified before that date
• On average, how long have silicon qualification cycles and board-level errata mitigation taken on your last two platform programs Options: <3 months, 3-6 months, 6-12 months, 12-18 months, >18 months
• Would you accept an accelerated qualification that reduces test scope to meet the freeze date if we agreed a remediation plan for the remaining tests Options: Yes, for critical tests only, Yes, with contingency and escrow, No, full qualification required, Unsure
• When was the last time a part shortage or long lead caused you to change a chosen silicon, and what did that cost in time or design rework

Integration readiness and resource constraints

• What single dependency or internal capability, if missing, would prevent you from completing an evaluation board integration within 12 weeks Options: Access to vehicle network topology, Diagnostic firmware access, Dedicated lab bench time, Qualified connectors and cables, No missing dependencies, Other
• Who currently owns the test environments and access to vehicle-level CAN, CAN FD, LIN, and Ethernet domains required to reproduce your topology Options: Your hardware lab, OEM central lab, Tier 1 partner lab, Third-party lab, No clear owner yet
• Are the APIs, diagnostic logs, and firmware access we need already available to outside evaluation teams, or will restricted access slow work Options: Fully available, Available with NDA, Limited access, Not available
• Estimate the number and specialties of engineers your team can commit to hands-on hardware integration and debugging during the evaluation

What other options you are weighing

• Name the incumbent supplier, internal program, or fallback option you would revert to if there were unresolved silicon issues, and explain why that option would win
• Please list the alternatives you are actively evaluating, such as incumbent multi-protocol families, single-protocol vendors, startups focused on Ethernet, or internal gateway development Options: Incumbent multi-protocol vendor, Single-protocol families, Startups focused on Ethernet, Internal gateway development, Delay migration, Other
• If your current approach could meet acceptance criteria with minor board changes, would you prefer that over qualifying a new silicon family Options: Yes, minimize change and risk, No, prefer future-proof solution, Depends on cost and timeline, Unsure
• Identify who internally is advocating for an in-house software or gateway solution instead of qualifying new hardware Options: Systems architecture, Software platform team, Electronics platform group, Procurement, Other

Defining evaluation scope and success signals

• Specifically, which acceptance criteria would cause your team to sign off on a silicon for production and which of those are nonnegotiable
• Provide the numeric measurement thresholds you require for EMC, deterministic latency, and sleep-mode power on evaluation boards where available
• Walk me through the roles that will perform acceptance testing, who owns each qualification milestone, and who signs each milestone
• Would you accept a split validation approach where some tests run in lab and others run in a timeboxed in-vehicle pilot Options: Yes, split validation, No, full vehicle validation required, Partial split with OEM approval, Unsure
• Describe the handover artifacts and documentation you require at the end of evaluation to proceed to system integration

Decision triggers and next steps

• Assuming the evaluation demonstrates the required metrics, what internal approvals, budget signoffs, and procurement steps remain before you could commit to long-term supply
• Within what timeline would you expect to finalize commercial terms and part qualification milestones after prototype validation Options: Immediately (within 2 weeks), Within 1 month, 1-3 months, 3-6 months, Longer than 6 months
• Identify the operational or commercial risks that would make you delay production sign-off even if technical tests pass Options: Supply continuity, Unresolved errata, OEM spec changes, Certification delays, Cost increases, Other
• Rate your procurement organization's confidence that decade-long supply commitments can be enforced with current supplier contracts, from 1 low to 5 high Options: 1, 2, 3, 4, 5
• Could you run a time-boxed pilot build under an agreed errata handling protocol to accelerate commercial commitment Options: Yes, with defined scope, Yes, with warranty protections, No, not acceptable, Unsure

• Solution Experience Session — Verification & Gateway Bridging

• Confirm the current state and its cost
• You confirm the proposed evaluation-board workflows cover the latency, EMC, and sleep-power scenarios you need for silicon selection.
• Deliver a draft evaluation-board test matrix and gateway bridging test plan within 7 business days.
• You confirm the gateway bridging test reproduces your interoperability risk and the proposed mitigation is acceptable.
• Map your architecture goals to verification scenarios
• Provide the current vehicle network topology, critical timing constraints, and the platform freeze date.
• Provide any existing EMC, latency, or sleep-mode acceptance thresholds you must meet, and any AUTOSAR or OPEN Alliance conformance notes.
• You agree on the remaining qualification evidence and which artifacts are required to meet the platform freeze decision points.
• Walk one evaluation-board workflow end to end
• Schedule the hands-on hardware evaluation session on mutually available dates within the next 10 business days.
• You validate the timeline impact and accept the next-step delivery dates for hands-on evaluation.
• Demonstrate a gateway bridging interoperability case
• Align acceptance criteria and responsibilities
• Identify the internal stakeholders who must sign off on qualification artifacts and their decision gate dates.
• Validate that this matches your imperative

• Solution Experience Session — Verification & Gateway Bridging
• Solution Experience Deck
• Solution Brief - Verification & Integration Plan

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• slides
• document

• Deliver multi-protocol transceiver ICs
• Deliver automotive Ethernet PHYs
• Deliver automotive Ethernet switch ICs
• Deliver gateway processor ICs (CAN-to-Ethernet)
• Ship evaluation board with reference firmware
• Deliver AUTOSAR-compliant driver and diagnostic stack
• Deliver unified diagnostic interface firmware package
• Deliver AEC‑Q100 production parts and qualification kit
• Provide ISO 26262 safety documentation package
• Deliver silicon errata and board-level workaround kit
• Deliver EMC-hardened reference PCB layout and filter kit
• Deliver sleep-mode power profiles and firmware tuning
• Ship production-qualification sample lots
• Provide long-term production supply and allocation agreement

Deliver multi-protocol transceiver ICs

• Which protocols and maximum bitrates must the transceiver ICs support on your evaluation board (for example CAN FD 8 Mbit/s, Classical CAN 1 Mbit/s, LIN 20 kbit/s)? Options: Classical CAN 1 Mbit/s, CAN FD up to 8 Mbit/s, LIN 20 kbit/s, Single-wire CAN, Other
• Identify the required isolation and voltage domains for the transceiver in your ECU reference design (for example 12 V battery domain, 24 V commercial vehicle domain, or galvanic isolation needed). Options: 12 V domain, 24 V domain, Galvanic isolation required, No isolation required, Other
• State the target electromagnetic compatibility standard and test level you will validate the transceiver against on the evaluation board (for example CISPR 25 Class 5, ISO 11452-2). Options: CISPR 25 Class 5, CISPR 25 Class 3, ISO 11452-2, Custom/test-lab spec
• Provide the acceptable sleep-mode current threshold for the transceiver measured on the evaluation board (specify in microamperes, uA).
• Who will own pin-mapping and BOM decisions for the transceiver on your evaluation-board schematic? Options: Your hardware team, Joint working group, We will assign later

Deliver automotive Ethernet PHYs

• Select the PHY speeds you require on the evaluation board (for example 100BASE-T1, 1000BASE-T1, 10BASE-T1S). Options: 100BASE-T1, 1000BASE-T1, 10BASE-T1S, Other
• Indicate the required physical-layer interface components for the PHY on the reference PCB (for example MDI magnetics, specific common-mode choke values, connector style). Options: MDI magnetics, Common-mode choke specified, Direct MDI (no magnetics), Other
• List OPEN Alliance conformance test profiles or specific test cases the PHY must pass during your evaluation (cite the test profile or clause).
• Provide the maximum allowed PHY-induced latency per hop in microseconds for your zonal Ethernet architecture. Options: < 10 µs, 10-50 µs, 50-200 µs, Custom
• Specify any required PHY features for in-vehicle serviceability (for example MDIO management, power-down modes, wake-on-LINK). Options: MDIO required, Power-down modes required, Wake-on-LINK required, No special features

Deliver automotive Ethernet switch ICs

• Define the required port count and port types on the switch IC for your gateway prototype (for example 1x 1000BASE-T1 uplink, 4x 100BASE-T1 downstream). Options: 1x 1000BASE-T1 + 4x 100BASE-T1, 4x 100BASE-T1 only, 2x SGMII + PHY ports, Custom
• Describe the required quality-of-service and cut-through latency thresholds per port for in-vehicle control messages (provide target in microseconds).
• List the IEEE and TSN features the switch must support during your verification (for example IEEE 802.1Q, 802.1AS, 802.1Qbv). Options: 802.1Q VLAN, 802.1AS time sync, 802.1Qbv time-aware shaping, 802.1CB frame replication
• Assign who will define switch ACLs, MAC provisioning, and priority mappings during evaluation. Options: Your network team, Shared working group, We will assign later
• Estimate the forwarding table size and multicast group count the switch must sustain during gateway interoperability tests. Options: < 1k entries, 1k-10k entries, > 10k entries, Custom

Deliver gateway processor ICs (CAN-to-Ethernet)

• List the gateway use cases you will validate on the gateway processor (for example CAN-to-Ethernet bridging, CAN tunneling over Ethernet, SOME/IP translation). Options: CAN-to-Ethernet bridging, CAN tunneling over Ethernet, Protocol translation to SOME/IP, Other
• Which AUTOSAR stack variant must be supported on the gateway (specify AUTOSAR Classic Platform, AUTOSAR Adaptive, or custom middleware)? Options: AUTOSAR Classic Platform, AUTOSAR Adaptive, Custom middleware, No AUTOSAR
• Provide the maximum allowable end-to-end latency for a bridged CAN message across the gateway prototype including serialization and PHY delays (specify in milliseconds or microseconds).
• Indicate required diagnostic mapping behavior between CAN DTCs and Ethernet-side diagnostics for the gateway evaluations.
• Identify who will supply or maintain the gateway reference firmware used for protocol bridging tests. Options: Your firmware team, Shared working group, We will assign later

Ship evaluation board with reference firmware

• Which evaluation-board form factor and external connectors do you require to integrate with your ECU test harness (for example 40-pin header, RJ45 for 100BASE-T1, OBD interface)? Options: 40-pin header, RJ45/100BASE-T1 connector, OBD connector, Custom
• Provide the list of preloaded reference firmware features you need on delivery (for example bootloader, diagnostic CLI, CAN logger, Ethernet packet capture, power profiling utilities). Options: Bootloader, Diagnostic CLI, CAN logger, Ethernet packet capture, Power profiling
• Specify the toolchain and version required to build the reference firmware so it matches your continuous-integration environment (for example GCC version, cross-compiler).
• Explain how you will validate secure boot and firmware cryptographic signing behavior on the evaluation board (for example test vectors, HSM integration, signature verification report).
• Where should the initial evaluation boards be shipped for on-site testing (for example your integration lab, an accredited third-party lab, or a designated pilot line)? Options: Your integration lab, Third-party test lab, Pilot production line

Deliver AUTOSAR-compliant driver and diagnostic stack

• Which AUTOSAR release and platform must drivers conform to (specify release number and Classic or Adaptive platform)?
• Specify the diagnostic services and UDS (Unified Diagnostic Services) mapping required for the driver stack on your ECU.
• Provide the acceptable ECU boot-time budget with the AUTOSAR stack present on the evaluation board (specify in milliseconds). Options: < 100 ms, 100-500 ms, > 500 ms, Custom
• Which integration artifacts must accompany the driver package (for example ARXML, RTE configuration, BSW mapping)? Options: ARXML files, RTE configuration, BSW mapping, Build scripts
• Who will own integration of the AUTOSAR stack into your existing ECU runtime environment (RTE)? Options: Your integration team, Joint integration team, We will assign later

Deliver unified diagnostic interface firmware package

• List the diagnostic transports that must be supported by the unified diagnostic interface (for example CAN, CAN FD, Diagnostics over IP (DoIP)). Options: CAN, CAN FD, DoIP (Diagnostics over IP), LIN
• Provide the expected format for DTC root-cause traceability in diagnostic logs produced by the firmware (for example JSON trace, ASTM-like matrix, proprietary CSV).
• Which transport-layer security requirements apply to DoIP sessions on the evaluation board (for example TLS version, mutual authentication, certificate management)? Options: TLS 1.2, TLS 1.3, Mutual TLS required, No TLS required
• Do you require a hosted web-based diagnostic portal bundled with the firmware for remote analysis of captured sessions? Options: Yes, No
• Who will maintain firmware updates, packaging, and over-the-air (OTA) delivery format for the diagnostic interface during the evaluation period? Options: Your SW team, Shared SW maintenance, We will assign later

Deliver AEC‑Q100 production parts and qualification kit

• Which AEC-Q100 device grade and temperature range do you require for your program (specify grade and min/max temperature)? Options: Grade 0 (‑40 to 150°C), Grade 1 (‑40 to 125°C), Grade 2 (‑40 to 105°C), Custom
• Provide the production-qualification sample count and lot distribution you require for vehicle-level validation (for example number of DUTs per lot and number of lots).
• What acceptance criteria will confirm the production parts meet AEC-Q100 stress tests such as temperature cycle, HAST, and mechanical shock?
• Specify the traceability and labeling data that must accompany each qualification kit lot (for example lot code, wafer fab traceability, date code).
• Who will run or witness the AEC-Q100 qualification tests and where should those tests be performed (for example your lab, third-party lab, or supplier fab)? Options: Your lab, Third-party lab, Supplier fab, Witness by joint team

Provide ISO 26262 safety documentation package

• What ISO 26262 target Automotive Functional Safety level (ASIL) must the documentation support for the device (for example ASIL A, B, C, or D)? Options: ASIL A, ASIL B, ASIL C, ASIL D
• Which safety artifacts must be included in the package (for example Safety Manual, FMEDA, Safety Plan, Safety Case)? Options: Safety Manual, FMEDA, Safety Plan, Safety Case, All listed
• Provide the contact and role of the safety owner or assessor who will accept the FMEDA and related safety artifacts.
• How must traceability between hardware failure modes and system-level safety goals be presented (for example FMEA matrix, requirements traceability matrix)? Options: FMEA matrix, Requirements traceability matrix, Other
• When do you need the ISO 26262 package delivered relative to your platform freeze date (for example at evaluation start, before silicon selection, or before design lock)? Options: At evaluation start, Before silicon selection, Before design lock

Deliver silicon errata and board-level workaround kit

• List the categories of silicon errata you need proactively documented before design lock (for example timing, PHY inrush, ECC limitations, boot ROM issues). Options: Timing, PHY inrush, ECC limitations, Boot ROM issues, Other
• Provide the form you expect board-level workaround guidance to take (for example schematic change, BOM change, firmware patch note, measured regression tests). Options: Schematic change, BOM change, Firmware patch note, Regression test report
• What evidence will validate that a board-level workaround resolves the erratum on your evaluation board (for example reproducible test steps, regression test vectors, sign-off report)?
• Estimate the maximum acceptable impact window for an erratum resolution measured from report to confirmed workaround (specify in calendar months). Options: < 1 month, 1-3 months, 3-6 months, > 6 months
• Name the escalation contact and preferred SLA for critical errata in your program.

Deliver EMC-hardened reference PCB layout and filter kit

• Which EMC standards must the reference PCB layout target for vehicle-level radiated and conducted emissions testing (for example CISPR 25, ISO 11452)? Options: CISPR 25, ISO 11452, Both CISPR 25 and ISO 11452, Other
• Provide the specific filter components and recommended placement constraints you require in the filter kit (for example common-mode choke value ranges, capacitor types, recommended footprints).
• Specify the chassis and cable-harness configurations that must be considered when validating the reference PCB in EMC tests. Options: Vehicle chassis mimic, Standard harness length (1 m), Custom harness - specify
• How will you measure EMC radiated emissions on the delivered reference PCB (for example pre-compliance chamber, accredited test lab, and acceptance limits)? Options: Pre-compliance chamber, Accredited test lab, Internal EMI bench
• Do you require Gerber, ODB++, and placement files compatible with a specific PCB CAD tool (specify tool if required)? Options: Yes - specify tool, No - generic Gerber ok

Deliver sleep-mode power profiles and firmware tuning

• Provide the target sleep-mode current per ECU you expect measured on the evaluation board (specify value in microamperes, uA).
• Which sleep-entry and wake-up sequences must the firmware support during power characterization (for example CAN wake from bus activity, LIN wake, magic packet over Ethernet)? Options: CAN bus wake, LIN wake, Ethernet magic packet, GPIO wake
• How will you accept measured sleep-mode power results (for example a power measurement report with test jig description, averaging method, and sample count)?
• Specify the allowed wake-up latency budget from sleep to full ECU operation required by your integration tests (specify in milliseconds). Options: < 10 ms, 10-100 ms, > 100 ms, Custom
• Who will run the power characterization and provide measurement fixtures and logs during the evaluation phase? Options: Your power lab, Third-party power lab, Supplier provides data

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• Purchase Agreement
• Order Confirmation
• Part Qualification Milestone Schedule
• Errata & Workaround Protocol
• Long-Term Supply Agreement
• Price & Volume Commitment Schedule
• Automotive Compliance Addendum
• Change Control & Obsolescence Policy
• Production Acceptance Certificate
• Warranty & Returns

• Go-live Health Check (weeks 1-4)
• First Measurement Review (weeks 4-10)
• Acceptance Gate Meeting (≈ day 90)
• Post-Acceptance Stabilization and Errata Burn-down (day 120-180)
• Quarterly Operational Review (ongoing)

• Publish an errata closure tracker with expected resolution dates and test validation criteria.
• Confirm the incumbent wind-down approach and archival actions are assigned and scheduled.
• Publish the acceptance decision record including all test artifacts and the signatory statement.
• If conditional acceptance, publish the remediation plan with specific tests, owners, and closure dates.
• Execute the incumbent decommissioning tasks or document the read-only retention plan and archive locations.
• Errata status and burn-down plan
• Reduce open silicon errata to the agreed target and document expected resolution dates for remaining items.
• Confirm pilot production yield meets or has a clear remediation plan relative to Integration & Launch targets.
• Agree specific firmware or board-change deliverables and verification windows for closure.
• Reconfirm acceptance criteria and owners
• Schedule firmware and board-change verification windows and reserve pilot build slots for re-validation.
• Produce a supply-risk mitigation plan for any long-lead components flagged as at-risk.
• Production incidents and trend analysis
• Keep high-severity incident rate trending down and ensure no critical regressions remain open.
• Maintain a declining count of open errata workarounds with clear closure dates.
• Validate that supply forecast meets the production ramp needs or document agreed mitigation actions.
• Update the incident and errata dashboards with remediation status and open action owners.
• Deliver a quarterly supply-risk report highlighting any changes to committed allocations.
• Document any agreed escalation steps for high-priority engineering changes.
• All acceptance criteria from Evaluation Scope are confirmed with named owners.
• Critical deployment blockers are identified and have assigned remediation actions with target dates.
• Schedule and data sources for the First Measurement meeting are agreed.
• Publish a deployment checklist status and access details for evaluation boards and prototypes.
• Log all open blockers with severity, temporary workarounds, and target resolution dates.
• Confirm telemetry sources and data export format for the First Measurement session.
• Measurement methodology and data integrity
• Confirm the first measurement dataset is valid and traceable to raw test artifacts.
• Document corrective actions for each metric not meeting targets in Evaluation Scope, with owners and dates.
• Confirm the expected date for the Acceptance Gate meeting and required deliverables.
• Publish the measurement report with raw artifacts, test logs, and the reconciliation to Evaluation Scope targets.
• Create remediation tickets for each failing metric including test plan for re-validation.
• Schedule follow-up test windows and reserve evaluation board time for re-test runs.
• Restate acceptance criteria from Evaluation Scope
• Produce a documented pass/fail decision for every acceptance criterion listed in Evaluation Scope.
• Capture a formal acceptance decision with named signatory or a documented conditional-acceptance closure plan.
• Deployment and pilot validation
• Open errata and workaround status
• Present outcome data per acceptance criterion
• Present sleep-mode current results
• Pilot production yield review
• Board-level workarounds and firmware patches
• Document pass/fail per criterion
• Supply continuity update
• Present end-to-end latency results
• Early operational signals
• Supply continuity and long-lead items
• Open issues triage
• Diagnose gaps and root causes
• Enhancement requests and escalation items
• Incumbent decommissioning checkpoint
• Immediate remediation actions and cadence
• Agree corrective actions and timeline to acceptance gate
• Formal acceptance decision and signatory capture