How your team currently verifies its biggest blocks

• How long has your team been using your current verification flow for the blocks you want to evaluate? Options: Under 6 months, 6-12 months, 1-3 years, 3+ years
• Describe the primary block or subsystem your team plans to run on the platform, including approximate gate count and top-level functionality.
• Who on your team will own the evaluation day-to-day and who signs off on results? Options: Verification Manager, Lead Verification Engineer, VP Engineering, Program Manager, Other
• Approximately how many existing testbenches and pieces of verification IP in your environment would need migration for a representative pilot? Options: <50, 50-200, 200-1000, 1000+
• What is your target timeline to reach a go/no-go decision for this evaluation? Options: Within 2 weeks, Within 4 weeks, Within 2 months, 3-6 months, No fixed timeline

Which remaining gap could repeat a costly respin

• If your last silicon respin cost $5M and three months, which remaining verification gap in your current flow would repeat that outcome?
• List the coverage metrics your team tracks now, and indicate which are below your sign-off threshold. Options: Functional coverage, Code coverage, Assertion coverage, Toggle/structural coverage, System-level scenarios
• How often do your full regression runs complete within the window your team needs to iterate on detected bugs? Options: Always within window, Often within window, Sometimes missed, Rarely within window
• Which debug tasks consume the most engineer-hours for your team when a system-level bug appears? Options: Trace capture, Signal tracing, Cross-platform breakpoint setup, Firmware replay, Root-cause analysis
• If our platform closed 10 percentage points of coverage and found at least one system-level bug your current flow missed, could your organization commit to a paid pilot within the same quarter? Options: Yes, commit within quarter, Need leadership approval, Depends on contract, No, need more data

What will slow or stop a migration in your organization

• Who inside your organization would block a switch to a new emulation platform for your verification flow, and why? Options: Engineering leadership, Procurement, Legal/IP, Program management, Other
• Tell me about the largest migration risk your team foresees when moving thousands of testbenches to a new platform.
• Estimate the number of engineers your organization would need to port and validate the testbenches for a single large block. Options: <2, 2-5, 6-10, 10-20, 20+
• Which access or IP restrictions in your setup typically slow down external partner work for your verification projects? Options: Third-party IP licenses, NDA constraints, Export control, Proprietary firmware, Data classification
• Could legal or data-access approval timelines in your organization over six weeks prevent the pilot from starting? Options: Yes, would block, Maybe, depends on timeline, No, will not block

Which alternatives are on your shortlist, and why

• Name the alternative your team is most seriously considering and explain why it could win this decision. Options: Incumbent vendor, Internal extension of current tools, Open-source tooling, Other commercial vendor, Custom in-house development
• List the internal options your team has proposed, including timelines and estimated cost to scale them to full-chip runs. Options: Rewriting testbenches, Buying more simulators, Investing in formal tools, Hiring contractors, Other
• Describe the incumbent verification approach your team would need to see materially improve to stay with it instead of changing vendors.
• What single commercial or technical outcome would make your organization abandon an internal fix-it-yourself plan? Options: Cost parity vs internal build, Proven runtime improvement, Clear bug-find advantage, Lower total migration cost
• Suppose the incumbent matched the emulation capacity and cost your procurement team models, would your decision process change? Options: Yes, we would stay with incumbent, No, we would still evaluate, Depends on proven debug workflow

Can your team and systems move this quickly

• Are you prepared to give external engineers testbench and firmware access for your pilot within four weeks, or will internal approvals block that timeline? Options: Yes, within 2 weeks, Yes, within 4 weeks, No, approvals needed >4 weeks, Access restricted, cannot provide
• Identify the APIs, tooling, or integration endpoints in your environment that our platform must connect to, and who on your team owns them. Options: REST APIs, Proprietary adapters, SSH/SFTP, Custom transport, No APIs available
• Estimate whether your current network and secure enclave capacities can host an emulation array for your pilot, and describe any constraints. Options: Yes, sufficient, Maybe with upgrades, No, network constrained, Need on-prem hardware
• Provide the named system owner and the legal point of contact in your organization for data-access approvals.
• Could missing formal IP licenses or export restrictions in your setup block a pilot? Options: Yes, could block, Depends on IP, No, unlikely to block
• Would a lack of two full-time verification engineers from your team force you to pause the evaluation rather than run a scaled pilot? Options: Yes, would pause, We can assign engineers, We can provide part-time support, Unsure

Which pilot outcomes move you to rollout

• Where would your team draw the line on acceptance metrics that must be met to proceed to rollout? Options: Coverage >=95%, Coverage >=90% plus bug find, Bug discovery vs current flow, Runtime equal or better than current
• Provide the specific sign-off metrics your team requires for coverage, runtime, and bug discovery rate for the pilot. Options: Coverage percentage, Average runtime per run, Bugs found per 1000 runs, Time to root cause
• Specify the minimum number of representative testcases and firmware scenarios your team requires to pass in an acceptance run. Options: <100, 100-500, 500-2000, 2000+
• Calculate the debug productivity improvement, in hours saved per bug or per engineer per week, that would justify migration cost in your team's model. Options: 1-2 hours per bug, 3-8 hours per bug, >8 hours per bug, Not sure / do not model this
• Assuming the pilot meets your team's acceptance criteria, what is the fastest internal step that would move you to commercial negotiation? Options: Move to commercial negotiation immediately, Require one executive review, Require procurement approval, Need internal pilot evaluation
• Name the single missing acceptance metric that would stop your organization from signing a rollout contract. Options: Coverage shortfall, Missing debug features, Data access restrictions, Cannot meet runtime

How to get from pilot data to a yes

• When would your leadership expect to see pilot data before approving budget for a rollout? Options: Within 2 weeks, Within 4 weeks, By end of quarter, Longer than quarter, No expectation set
• Outline the approvals and sign-offs your team needs before a paid pilot can start, with typical lead times. Options: Technical lead sign-off, VP Engineering sign-off, Procurement approval, Legal NDA, All of the above
• Approximate the internal budget holder and procurement milestones your organization needs to convert a successful pilot into purchase within three months. Options: Central engineering budget, Project-specific budget, R&D funds, No budget identified
• Identify the names or roles in your procurement or legal teams that must be looped in early, and indicate if they can review an NDA within ten business days. Options: Yes, within 10 days, No, longer than 10 days, Unsure
• Would your team prefer a fixed-scope four-week technical pilot or a variable-scope discovery, and why? Options: Fixed-scope pilot, Variable-scope discovery, Open to either
• Indicate the single approval within your organization that would prevent signing a pilot SOW this week. Options: Budget approval, Legal sign-off, Data access approval, Resource commitment, Other

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• Deploy FPGA-Based Emulation Array
• Automatic RTL Partitioning and Mapping
• Migrate Simulation Testbenches to Platform
• Port Verification IP Libraries
• Integrate Firmware and Boot Software with Emulation
• Run Full Regression Suites on Emulation
• Execute Formal Property Verification Runs
• Merge Simulation, Emulation, and Formal Coverage
• Capture and Replay Debug Sessions
• High-Throughput Simulation Parallelization
• Onboard Engineers to Unified Debug Environment
• Full-Chip Emulation Bring-Up and Trace Export

Deploy FPGA-Based Emulation Array

• Which target gate capacity do you need the emulation array to support (estimate in gate equivalents)? Options: <10M gates, 10M-50M gates, 50M-200M gates, >200M gates
• How many concurrent full-chip instances do you need to run during peak regression windows? Options: 1, 2-3, 4-8, 9+
• Who will own rack-level provisioning and physical access for FPGA boards at your datacenter?
• When do you require air-gapped or on-premises deployment versus cloud-hosted arrays? Options: Immediate on-premises, Within 4 weeks, Pilot in cloud then on-premises, Cloud only
• Confirm any facility constraints (power per rack in kW, cooling type, network egress limits) in your target site.

Automatic RTL Partitioning and Mapping

• Provide the top-level RTL module names and approximate gate counts for the blocks you expect to partition.
• List critical clock and reset domains that must remain undisturbed by automatic partitioning.
• Do you require preservation of cycle-accurate interfaces for PCIe, DDR, or Ethernet during partitioning? Options: Yes, No, Partial (specify interfaces)
• Is there existing hand-partitioning or constraints files (for example, XDC or XML) we must honor? Options: Yes, No
• Specify acceptable insertion latency in cycles for cross-FPGA signals after partitioning. Options: 0 cycles, 1-5 cycles, 6-50 cycles, TBD

Migrate Simulation Testbenches to Platform

• Describe the number and type of your existing testbenches (UVM sequences, directed, constrained-random).
• How many individual simulation testbenches must be migrated for the evaluation phase? Options: <50, 50-200, 200-1,000, >1,000
• Which simulator output formats do your testbenches produce for waveform and coverage collection (for example VCD, FSDB, WLF)? Options: VCD, FSDB, WLF, Other
• Are there proprietary DPI or foreign-language models used by your testbenches that need porting to the emulation environment? Options: Yes, No
• Who are the named owners for each testbench block for migration handoff and verification sign-off?
• Attach or list any recurring UVM sequences that must be preserved verbatim for debug equivalence.

Port Verification IP Libraries

• Identify the verification IP protocols you use (for example DDRx, PCIe, USB, I2C, SPI, Ethernet) and their versions. Options: DDR2/3/4/5, PCIe Gen1-Gen5, USB 2/3, I2C/SPI, Ethernet 1G/10G/25G, Other
• Do you have licensed third-party VIP with redistributable binaries or source that must be ported into the emulation host environment? Options: Yes, No
• Provide the number of VIP instances and whether they run as bus functional models or full protocol engines. Options: <10 instances, 10-50, 50-200, 200+
• List compliance tests or protocol checkers you require to remain enabled during emulation runs (for example link training, assertion suites).
• Specify any proprietary PLI/DPI bindings or license files needed to execute your VIP under emulation.

Integrate Firmware and Boot Software with Emulation

• How will you provide firmware and boot images for emulation (for example NFS, network boot, local flash images)? Options: NFS, Network boot (TFTP), Local image upload, Other
• State expected firmware image sizes in megabytes and boot time targets in seconds for system bring-up.
• Estimate the number of OS kernels or bootloaders (for example U-Boot, bare-metal images) that must be integrated into emulation. Options: 1, 2-3, 4-10, 10+
• Confirm whether your firmware requires debug stubs such as a GDB server or kernel debug symbols during emulation debug sessions. Options: Yes - GDB server, Yes - symbols only, No
• Indicate any board support package or hardware abstraction layer dependencies that must be adapted for FPGA prototypes.
• Attach a sample boot log or failure mode that we can use to validate end-to-end boot reproducibility on the emulation array.

Run Full Regression Suites on Emulation

• Describe the regression duration and parallelization strategy you currently run for your largest block (for example hours per job, CI parallel jobs).
• How long is a representative full regression on simulation today and what target runtime do you expect on emulation?
• Is cycle-accurate trace capture required for failing regression runs and what trace depth do you require (for example cycles or millisecond window)? Options: Cycle-accurate, Transaction-level only, Both, None
• Identify acceptance criteria for the evaluation run (for example target coverage increase in percentage points, minimum critical bugs found, maximum runtime) that will define success.
• Indicate the subset of testcases you want run during the time-boxed evaluation (for example smoke, regression, system integration). Options: Smoke tests, Block regression, Full system regression, Custom subset
• Upload the current regression manifest or paste a sample testlist that maps tests to DUT blocks for migration planning.

Execute Formal Property Verification Runs

• State the number of formal properties and proof harnesses planned for the proof runs. Options: <100 properties, 100-1,000, 1,000-10,000, >10,000
• Enumerate sequential corner cases such as reset sequences and power state transitions that are highest priority for proofs.
• Are there existing formal assumptions or deadlock detectors in your property set we must preserve? Options: Yes, No
• Define time-box or CPU-hour limits we should apply to automated proof attempts per property. Options: 5 minutes, 30 minutes, 2 hours, Custom (specify)
• Upload examples of failing assertion traces or counterexamples you consider must be resolved during evaluation.

Merge Simulation, Emulation, and Formal Coverage

• Summarize your current coverage model artifacts (for example functional coverage bins, covergroups, assertion coverage CSVs) and where they are stored.
• What unified coverage metrics (for example toggle coverage percentage, crossing coverage counts, assertion hit rates) will you use to accept the evaluation?
• Name the storage and metadata formats you use for coverage dumps for ingestion (for example .ucdb, .cov, csv). Options: .ucdb, .cov, .csv, Other
• How will you map coverage bins from simulation and formal runs to system-level bins for cross-run delta analysis?
• Paste a recent coverage report or summary that demonstrates your current baseline and gaps.
• Name the owner for final sign-off on merged coverage artifacts and describe the evidence that will validate acceptance (for example 95% block coverage, no open critical assertion failures).

Capture and Replay Debug Sessions

• Will you require cycle-accurate capture or transaction-level traces for debug replay? Options: Cycle-accurate, Transaction-level, Both, None
• Where should captured traces be stored and what maximum file size is acceptable per trace in gigabytes?
• Explain how replay determinism is validated today (for example seed control, scoreboard reconciliation) for failing tests.
• What debug interfaces must be exposed during capture and replay (for example JTAG, UART logs, PCIe TLP) and at what bandwidth?
• Document retention and redaction requirements for debug artifacts, including any IP-sensitive waveform segments that must be masked.

High-Throughput Simulation Parallelization

• Outline your current simulation parallelization approach including per-job CPU count and whether you use distributed runners or cloud burst.
• Estimate average per-test memory and CPU needs for your largest RTL regression jobs. Options: <4 GB / 1 vCPU, 4-16 GB / 1-4 vCPU, 16-64 GB / 4-16 vCPU, >64 GB / >16 vCPU
• Will you permit test splitting by DUT block or must regression runs remain top-level only? Options: Allow block-level splitting, Top-level only, Hybrid
• Select preferred orchestration for parallel runs for integration with your toolchain. Options: On-prem scheduler (for example LSF), Kubernetes, CI runner (for example Jenkins/GitLab), Other
• Define maximum acceptable variance in per-test runtime when parallelized (for example 5% standard deviation) for reproducibility. Options: <5%, 5-15%, 15-30%, >30%

Onboard Engineers to Unified Debug Environment

• How will you structure training cohorts for your verification engineers (for example per-block, role-based, train-the-trainer) and how many engineers per cohort?
• Inventory the IDEs and debug plugins your team uses that must be supported (for example waveform viewer, UVM sequence debugger).
• Does your team require hardware hands-on sessions for FPGA board-level debug as part of onboarding? Options: Yes, No
• When do you want role-based access and walkthrough sessions scheduled during the pilot? Options: Week 1 of pilot, Week 2, After initial bring-up, Custom schedule
• Outline the key learning objectives for the training (for example firmware bring-up, assertion triage, waveform navigation).
• Document success criteria for engineer onboarding (for example number of trained engineers, observed debug tasks completed) that will allow us to close the onboarding module.

• Mutual Confidentiality & Data Access Authorization
• Master Services Agreement (MSA)
• Statement of Work (SOW)
• Order Form / Subscription Agreement
• Service Level Agreement (SLA)
• Data Processing Agreement (DPA)
• Acceptance Criteria & Test Plan Annex
• Readiness & Resource Commitment
• IP Rights & Deliverables Addendum
• Change Order and Scope Management Procedure

• Go-live Health Check
• First Measurement Review
• Acceptance Gate Review (Day 90)
• Quarterly Operational Review

• Update the operational runbook and escalation contacts based on lessons from the quarter.
• Restate acceptance criteria and numeric targets
• Produce a documented pass or fail for each numeric acceptance criterion recorded in Solution Scope with a signatory decision.
• Agree and time-box remediation tasks for any conditional or failed criteria with completion dates.
• Confirm the incumbent system wind-down plan and data archival status to avoid dual-system persistence.
• Publish the acceptance decision document with pass/fail status for each criterion and archive it in the shared workspace.
• Create a remediation tracker for conditional failures with clear validation steps and deadlines.
• Execute the agreed incumbent decommission or read-only retention tasks and confirm data archival completion.
• Coverage reporting and trend analysis
• Confirm coverage convergence percent and emulation capacity utilization remain within acceptable ranges defined in Solution Scope.
• Reduce the count of open critical defects and high-priority enhancement requests according to agreed timelines.
• Agree any support cadence or reporting changes required to keep the buyer operationally effective.
• Publish the quarterly coverage and capacity report with annotated trends and next-step recommendations.
• Prioritize and schedule the top enhancement requests and defects for the next operational window with verification steps.
• Re-confirm success criteria and owners
• All critical deployment blockers are listed with an owner and target resolution date.
• Access and onboarding gaps preventing early usage are identified and a remediation plan is agreed.
• Owners confirm where numeric acceptance criteria are recorded in Solution Scope for later measurement.
• Produce and circulate a deployment validation report listing environment status, migrated testbenches, and outstanding access issues.
• Log and prioritize critical blockers in the shared issue tracker with target resolution dates.
• Enable missing credentials and confirm connectivity for any engineers who reported access problems.
• Present first-data dashboard
• Determine whether coverage closure rate and bug discovery rate are trending toward the targets recorded in Solution Scope.
• Identify 2 to 3 root causes for any metric gaps and agree corrective actions with resolution dates.
• Confirm the remediation timeline that will be validated at the acceptance gate.
• Run focused benchmark runs on the named representative blocks to isolate runtime and coverage differences.
• Adjust RTL partitioning parameters and revalidate a failed testbench where partitioning is suspected to cause coverage loss.
• Update the shared dashboard with the new run results and annotates for root-cause findings before the acceptance gate.
• Deployment and migration validation
• Emulation capacity and run-time efficiency
• Diagnose gaps and root causes
• Present outcome data against each criterion
• Agree corrective actions and timelines
• Document pass or fail per criterion and capture signatory decision
• Open defects and enhancement request backlog
• Early adoption signals and usage patterns
• Confirm readiness timeline to acceptance gate
• Blockers and open issues with owners
• Agree remediation items and resolution timeline
• Operational support and cadence adjustments
• Incumbent wind-down and data disposition
• Agree immediate remediation actions