The failed lot, in plain facts

• Tell me about the tapeout and production lot that returned lower yield, including the product family, mask set count, and tapeout date
• Approximately how large was the observed yield gap for that lot Options: < 3%, 3–5%, 5–8%, 8–12%, > 12%
• Which failure analysis artifacts linked the yield loss to lithography or CMP issues, for example SEM images, patterned wafer maps, or cluster analysis summaries Options: SEM images, Wafer map clusters, Defect density heatmaps, Pattern correlation reports, Other
• Who on your team led the failure analysis and who owns follow-up investigations
• Walk me through the timeline from wafer return to decision to investigate — how many days elapsed and what were the major milestones

Where your signoff flow is letting yield through

• If DRC allowed the design to tape out but wafers failed, which specific signoff blind spot do you think is causing the biggest damage Options: Lithography hotspots not modeled, CMP-sensitive metal patterns, Via placement issues, Layer interaction/stack effects, Model calibration mismatch, Other
• Describe the most frequent pattern types you see on failed wafers, including layer, pitch, and surrounding context
• How many of the failing sites per million do you estimate the current flow detects versus how many you find in FA Options: < 50 per million, 50–200 per million, 200–1,000 per million, > 1,000 per million, Not measured
• Which manufacturing node and foundry process deck were used for that tapeout
• Which single technical gap, if resolved, would most reduce the risk of repeating this failure on your next mask run

How previous fixes have performed and what they cost

• Walk me through the last remediation cycle you ran for a yield-limiting pattern — what was changed and what was the outcome
• Roughly how many engineering hours did that cycle consume, from triage through verification Options: < 40 hours, 40–120 hours, 120–400 hours, > 400 hours, Not tracked
• When fixes were implemented, how often did they cause timing or routing regressions that required additional fixes Options: Almost always, Often, Occasionally, Rarely, Never recorded
• Who has final sign-off on layout fixes before masks are released, and how does that decision typically get made
• If an external analysis reduced false positives by 90%, how much engineering time would that realistically free up for your team this cycle Options: < 1 engineer-week, 1–2 engineer-weeks, 2–5 engineer-weeks, > 5 engineer-weeks

The other options you're weighing

• Which alternatives to an outside DFM analysis are you currently evaluating or have deployed, including internal tools, incumbent vendors, or foundry services Options: Internal scripts and pattern libraries, Existing DFM vendor, Foundry-provided checks, Open-source toolchain, No alternative evaluated yet, Other
• What would have to be demonstrably true about your current approach for you to decide not to change vendors now
• Has anyone on your team proposed solving the issue purely with in-house work without an external partner, and if so, who would own that effort Options: Yes, Design team, Yes, Yield Engineering, Yes, Foundry liaison, No internal proposal, Other
• What single risk or limitation in the incumbent or in-house option would force you to select an outside partner instead
• Which selection criteria matter most when comparing offers — accuracy, turnaround time, integration effort, cost, foundry calibration, or something else Options: Accuracy of hotspot detection, Low false positives, Turnaround time, Ease of integration, Foundry calibration pedigree, Price, Other

What must be true for an engagement to run at all

• Which missing artifact, approval, or technical capability would stop this project immediately Options: PDK or process deck not available, Wafer inspection/FA data unavailable, No API or access to layout repositories, Legal/data-sharing approvals pending, Insufficient engineering bandwidth, Other
• Do you have the PDK versions, GDS streams, and foundry process decks ready to share under NDA Options: All ready, Most ready, missing documents, Only some layers available, Not available
• Who owns data access within your organization and who can authorize cross-company sharing under NDA
• Which integration endpoints will we need to connect to for automated analysis runs, such as your layout repository, CI system, or yield database Options: Layout repo (GDS/CEL), CI/CD pipeline, Yield database, Inspection/FA image store, None of the above / manual exchange
• How much dedicated engineering time can you commit to the pilot for integration, calibration, and review over a 6–8 week window Options: < 1 engineer (part-time), 1 engineer (part-time), 1–2 engineers (part-time), 1 engineer (full-time) or equivalent, Multiple full-time engineers

What success looks like and how you'll measure it

• If a pilot identifies true yield-killing hotspots and shows a 50% reduction in wafer escapes for the targeted patterns, what would that outcome unlock for your organization
• Which concrete acceptance metrics should the pilot hit for you to consider it successful, for example hotspot true-positive rate, reduction in escape count, or engineering time saved Options: Hotspot true-positive rate (target %), Escape count reduction (absolute or %), Engineering hours saved, Integration readiness, Foundry calibration agreement
• Who must sign off on the pilot result to move into a broader deployment, and what is their primary concern (technical accuracy, schedule impact, or cost) Options: Director of Physical Design - technical accuracy, Yield Engineering Manager - schedule impact, VP Engineering - cost/ROI, Foundry liaison - calibration
• If the pilot proves the target metrics, what is the single operational or contractual obstacle that could still prevent you from approving full rollout that week
• How quickly would you want the pilot started, assuming approvals and data access are available Options: Immediately, Within 2 weeks, Within 1 month, Quarterly planning window

Decision, budget, and next steps

• Who on your team holds the final budget approval and what typical procurement steps are required to fund a pilot
• What is the approximate budget range you would allocate for a 6–8 week evaluation that includes analysis, a small optimization run, and a delivered report Options: <$25k, $25k–$75k, $75k–$150k, >$150k, Undisclosed
• Which timeline would force you to delay selection, for example pending a critical tapeout or quarterly freeze Options: Critical tapeout in next 2 weeks, Quarterly design freeze coming, Foundry audit scheduled, No blocking timeline
• What would you need to see in an engagement proposal to be comfortable signing within 14 days after the pilot Options: Clear acceptance criteria, Data security and NDA terms, Fixed scope and deliverables, Integration plan and owners, Pricing model
• Would you like the platform team to prepare a recommended pilot scope and readiness checklist based on your answers here Options: Yes, please prepare, Maybe, I need more internal alignment, No, we will draft our own

• Solution Experience — DFM Analysis Mapping

• Confirm the current state and its cost
• You confirm the demonstrated workflow eliminates the specific post-silicon rework and yield variance described in Discovery.
• Provide a representative GDSII or OASIS tapeout segment, wafer failure locations if available, and the foundry process deck within five business days.
• You agree on the concrete calibration data and acceptance criteria needed to trust hotspot calls and fixes.
• Live mapping of DFM analysis to your tapeout
• Run the initial DFM analysis on the provided tapeout segment and deliver a prioritized hotspot report with proposed in-loop fixes within five business days of receiving files.
• You commit to providing a representative tapeout segment and foundry process deck so the seller can run a calibrated analysis.
• Demonstrate in-loop optimization and predicted impact
• Provide a short calibration plan that lists additional foundry data needed and estimated effort to align models with your process within three business days.
• Surface calibration needs and residual risks
• Identify the internal owners who will review hotspot reports and authorize integration tests.
• Validation checkpoint

• Solution Experience — DFM Analysis Mapping
• Solution Experience Deck
• Solution Brief

• meeting
• slides
• document

• Run foundry-calibrated lithographic hotspot scan
• Automated hotspot fix generation for place-and-route
• CMP-aware metal-fill optimization
• Via reliability optimization and redundancy insertion
• Calibrate ML models to customer wafer inspection data
• Deploy DFM plugin into place-and-route flow
• Export hotspot overlays in GDS and DEF formats
• Deliver prioritized yield-risk hotspot list
• Mask CD variability simulation for identified hotspots
• Produce CMP erosion and dishing risk maps
• False-positive suppression tuning with foundry models
• Integrate DFM flags into signoff reports and flows

Run foundry-calibrated lithographic hotspot scan

• Do you have the tapeout GDSII and associated DEF files for the lot to scan? Options: Yes, No
• Which foundry process node and PDK version should we use for the hotspot scan (provide exact PDK section or version string)?
• Provide the wafer inspection CSV or defect map you want correlated with hotspot locations (attach file path or describe export schema).
• Are optical proximity correction (OPC) model outputs or RET logs available to include in the scan (attach OPC/RET report if available)? Options: Yes, No
• Specify the reporting threshold you prefer for scan results (example choices: hotspots per million or top-N hotspots). Options: <=50 per million, 51-200 per million, >200 per million, Custom

Automated hotspot fix generation for place-and-route

• Do your place-and-route runs accept automated patch suggestions via DEF overlays or tool scripting interfaces? Options: Yes - DEF overlay, Yes - tool script, No
• Identify the placer tool and version that produced the current layout (provide exact tool and version string).
• List the timing slack budget constraints and the maximum allowed cell movement for automated fixes (for example: 10ns slack, 1 cell movement, or X nm).
• Provide any DEF keep-out regions or macros/hard-IP areas that must be excluded from automated fixes (attach keep-out DEF or description). Options: Yes - keep-outs attached, No keep-outs, Keep-outs exist but not attached
• Who on your team will review and sign off generated fix patches (name and role)?

CMP-aware metal-fill optimization

• Provide the metal stack and CMP recipe reference from your process deck or PDK that should be used for metal-fill analysis.
• List the GDS layers and current fill rules your signoff flow uses for metal-fill (attach rule excerpt if available).
• Have mask-level metal density constraints from your PDK or mask rules that must be enforced during optimization (attach excerpt)? Options: Yes, No
• Specify the CMP measurement thresholds you want reported (for example maximum dishing depth in nm or maximum affected area percentage).
• Would you like generated metal-fill overlays in GDS, or in-loop fill changes applied to the place-and-route run, or both? Options: GDS overlays, In-loop fill changes, Both, None

Via reliability optimization and redundancy insertion

• Identify the via types and layer transitions of concern in the failing lot (for example M1->M2, M2->M3) and list the layers.
• Have you collected pull-down test results or via failure distributions from wafer probe that can be correlated to layout sites? Options: Yes, No
• State the maximum allowable timing or area impact for adding via redundancy (for example percent cell area increase or timing slack budget).
• Attach any manufacturing keep-outs or power-mesh constraints in DEF that prevent additional vias in certain regions. Options: Attached, None, Exists but not attached
• Would you prefer automated via redundancy insertion during optimization or a flagged-priority list for manual placement? Options: Automated insertion, Flagged list for manual fix, Both

Calibrate ML models to customer wafer inspection data

• Confirm whether you have wafer inspection datasets available (CD-SEM outputs, optical defect maps with coordinates, or tool export) that we can use for calibration. Options: Yes, No
• Describe the file formats and schema of your inspection data (for example CSV defect map with X/Y, SEM images folder, database export).
• Attach or describe the lot-to-layout mapping file (reticle origin, die grid or die map) we should use to align inspection coords to GDS locations.
• What quantitative calibration acceptance criterion will confirm the ML model is calibrated (for example precision improvement at fixed recall, or reduction in false positives per million)? Options: Precision improvement target, False positives per million target, Custom - describe
• Who on your team can provide annotated defect samples and what turnaround can they commit to for supplying labeled examples?

Deploy DFM plugin into place-and-route flow

• Identify the place-and-route tool and exact version where the DFM plugin will be deployed (provide tool/version string).
• Does your environment expose a plugin API endpoint or scripting interface we should use (attach API docs or describe the interface)? Options: Yes - API docs attached, Yes - scripting only, No
• Indicate the CI/run schedule and compute environment for the plugin (for example nightly flows on an on-prem runner, per-checkin, or cloud VM). Options: Nightly, Per-checkin, On-demand, Other
• What acceptance test will verify successful plugin deployment (for example: plugin runs on provided sample layout and reports hotspots with no runtime errors)? Options: Successful run on provided sample without errors, Integration report and logs, Other - describe
• Describe credential, VPN, or artifact-storage access requirements needed for the plugin to run (include paths and access method).

Export hotspot overlays in GDS and DEF formats

• Select the overlay output you require for reviewer consumption: GDS layer overlays, DEF region comments, or both. Options: GDS overlays, DEF region comments, Both
• Should reviewers need visual markers tied to wafer coordinates, layout coordinates, or both? Options: Wafer coordinates, Layout coordinates, Both
• Indicate filename conventions and versioning tags required for overlays (for example lot_die_revision.gds).
• Will you require a mapping file between hotspot IDs and source layout coordinates (CSV) for issue-tracking import? Options: Yes, No
• Name the tool or viewer your reviewers will use to load overlays (provide viewer name and version).

Deliver prioritized yield-risk hotspot list

• Define the metrics that should determine hotspot prioritization (for example estimated failure impact, occurrence frequency per million, proximity to timing-critical nets).
• Select the output format(s) you require for the prioritized list (CSV with GDS coordinates, Excel with images, importable issue-tracker tickets). Options: CSV with coordinates, Excel with images, Issue tracker import, Other
• State the acceptance criteria that will confirm the prioritized hotspot list is specific (for example top N hotspots with repro images, suggested fixes, and location-mapped overlays). Options: Top 20 with images and suggested fixes, Top 50 with fixes, Custom - describe
• Name the owner on your side who will triage the prioritized list and indicate any SLA you expect for triage responses.
• Should each hotspot entry include a link to the suggested automated fix patch or only a remediation recommendation? Options: Link to patch, Recommendation only, Optional

Mask CD variability simulation for identified hotspots

• Attach the OPC/RET run files or model outputs required for mask critical-dimension (CD) variability simulation. Options: Attached, Not available
• Indicate mask stack and any phase-shift mask data that should be included in the simulation (provide file names or process deck references).
• State the statistical CD thresholds you use to flag unacceptable variability (for example sigma or ppm thresholds).
• Confirm whether per-hotspot simulated CD plots and pass/fail annotations are required in the simulation output. Options: Yes, No
• Upload any historical CD-SEM measurements we should use to validate simulation accuracy (attach sample files). Options: Attached, Not available

Produce CMP erosion and dishing risk maps

• Upload the layer stack and CMP recipe parameters (for example polishing time and slurry type) from your process deck.
• Choose die-level CMP risk maps, wafer-level aggregate heatmaps, or both for this engagement. Options: Die-level maps, Wafer-level heatmaps, Both
• Choose the export format for CMP risk maps (image overlays, CSV grid with coordinates, or GDS overlay). Options: Image overlays, CSV grid, GDS overlay, Other
• Enter the CMP measurement thresholds that should trigger remediation (for example dishing depth in nm or affected area percent).
• Confirm if you want suggested metal-fill remediation per hotspot included with the CMP risk maps. Options: Yes, No

False-positive suppression tuning with foundry models

• Upload any foundry-provided model parameters or historical false-positive counts that we should use for suppression tuning. Options: Attached, Not available
• Which baseline false-positive rate do you observe from your current DFM flow (provide numeric approximate: hotspots per million or range)? Options: <=100, 101-1,000, \, >1,000",, Unknown, ],, isMulti, : False}, {, section, : False,, content, :

• Non-Disclosure Agreement (NDA)
• Master Services Agreement (MSA)
• Statement of Work (SOW)
• Order Form / Subscription Agreement
• Software License & Deployment Rights
• Data Processing Agreement (DPA)
• Data Access Authorization
• Readiness Checklist and Authorization to Proceed
• Calibration & Foundry Model Addendum
• Service Level Agreement (SLA) and Support
• Change Order Agreement
• Deliverable Acceptance Certificate

• Go-live Health Check (weeks 1-4)
• First Measurement Review (weeks 4-10)
• Acceptance Gate — Outcome Review and Formal Acceptance (around day 90)
• Quarterly Success Review (ongoing)

• Schedule calibration or model-update windows for any new foundry process variants that require re-training or recalibration.
• Validate and document the data extraction and aggregation process used to compute the reported metrics.
• Restate acceptance criteria and numeric targets from Solution Scope
• Produce a documented pass or fail for each acceptance criterion recorded in Solution Scope with supporting evidence.
• Capture the buyer's named signatory for the acceptance decision in the meeting record.
• Confirm the incumbent system is either decommissioned or formally retained read-only and its data disposition is complete.
• Publish the formal acceptance record with criterion-level pass/fail, supporting evidence, and the buyer's named signatory.
• If any criterion failed, publish a remediation plan with concrete resolution dates and re-test windows.
• Document the incumbent wind-down steps taken and any remaining actions required to finalize decommissioning.
• Trend review for yield and hotspot remediation
• Verify that measured wafer yield delta (%) and count of prioritized hotspots fixed before mask commit remain at or improving toward the targets in Solution Scope.
• Ensure the backlog of enhancement requests and open issues is prioritized with clear next actions and timelines.
• Confirm ongoing calibration and data access plans to preserve measurement integrity for future quarters.
• Maintain a shared issue and enhancement request channel with status, priority, and expected resolution timelines.
• Produce and circulate the quarterly metric package that includes yield delta, hotspot fix counts, and false-positive rate.
• Reconfirm scope and acceptance criteria locations
• Confirm the deployment completed and the analysis engine produced initial runs without systemic failures.
• Surface and document critical blockers with agreed remediation tasks and target dates.
• Ensure all participants know where the numeric acceptance targets are recorded, in Solution Scope.
• Share deployment run logs and initial report outputs for asynchronous review.
• Publish a short remediation plan for any critical blockers with proposed resolution steps and target dates.
• Confirm contact list and escalation path for any production failures before the next measurement.
• Present first outcome data vs Solution Scope targets
• Determine whether measured wafer yield delta (%) and hotspot identification rate are moving toward the targets recorded in Solution Scope.
• Document root causes for any shortfalls and agree a targeted corrective action list with resolution timelines to reach the acceptance gate.
• Agree the data definition and reporting cadence for the acceptance gate comparison.
• Deliver a detailed metric package that includes wafer-level yield correlation, hotspot locations, and the false-positive investigation rate for the review window.
• Publish a corrective action list with expected completion dates to align with the acceptance gate schedule.
• Present final outcome data for each criterion
• Open issues and critical defect review
• Deployment and integration validation
• Root-cause analysis for metric gaps
• Document pass or fail per criterion and record acceptance decision
• Early adoption and usage signals
• Enhancement requests and backlog prioritization
• Agree corrective actions and timeline to acceptance gate
• Blockers and defect triage
• Data-quality and instrumentation checklist
• Operational health and instrumentation check
• Incumbent wind-down check
• Agree immediate remediation actions
• If applicable, agree remediation items and resolution timelines for any failed criteria
• Short status wrap and next steps