Technical evaluation and representative design

• To make the best use of your time, do you expect a hands-on technical evaluation to be required before full discovery? Options: Yes - run tools on a representative chip-package-board stack, Maybe - a light technical review or readout is enough, No - technical evaluation not required before discovery
• Is there a representative chip-package-board design available for analysis? Options: Yes - complete design files and layouts available, Partial - some files or models available, No - files are not available yet, Unsure
• What level of file and environment access can you reasonably provide for an evaluation? Options: Full file import and model access permitted, Access via controlled environment (SFTP, VPN, secure portal), Only summary data or exported reports, Unsure / requires internal approval

Cross-functional readiness

• Which roles would you expect to involve in a short technical evaluation? Select all that apply. Options: Packaging engineer, Die / physical design engineer, PCB / layout engineer, Thermal engineer, Power / PDN engineer, Program or project manager, Other
• Is there current alignment to involve die, package, and board teams together for this evaluation? Options: Yes - teams are aligned and available, Partially - some teams need internal coordination, No - teams are not aligned, Unsure

Budget

• Is there an allocated budget range for an initial technical evaluation? Options: <$10k, $10k–$50k, $50k–$150k, $150k–$500k, >$500k, No budget allocated / exploring options, Prefer not to say

Decision authority and timeline

• Who would sign off to authorize a paid technical evaluation (role or team)? Options: Director / Head of Packaging, VP Engineering, Program manager or PMO, Procurement / Finance, Not sure / needs to confirm, Other
• What target date or project milestone should the evaluation align to? Options: Within 2 weeks, Within 1 month, 1–3 months, 3–6 months, No fixed date / exploratory
• Would you like us to propose a brief agenda and a checklist of required files to make a technical evaluation productive? Options: Yes - please propose and book a short discovery meeting, Maybe - send the checklist first, No - not at this time

Your target electrical and thermal outcomes

• Which product family or design node is this evaluation scoped to? Options: New chip architecture, Derivative of an existing chip, Platform-level integration (chiplet/HBM), Other
• Tell me about the electrical targets you are optimizing for, for example eye mask, timing margin, or bit error rate
• How many thermal targets are you tracking and which are most critical, for example die hotspot, package case temperature, or board ambient limits? Options: Die hotspot, Package case temp, Board ambient, Thermal gradient across chiplets, Other
• Walk me through the baseline SI, PDN, and thermal numbers you expect the co-design to improve, with the most important metric first
• Who on your team will own final acceptance of the evaluation results and write the acceptance note? Options: Director of Packaging, VP Physical Design, Head of System Engineering, Cross-functional committee, Other
• If the pilot shows a 50% reduction in first-pass SI failure risk, what decision or funding would that likely unlock on your side?

Where late package decisions have historically created rework

• What's the most recent example where package or interposer parasitics surprised you, and what did it cost in schedule or masks?
• Describe the failure mode in that example, for instance timing margin loss, unexpected crosstalk, or PDN resonance Options: Timing margin loss, Excessive crosstalk, PDN resonance, Thermal hotspot, Other
• When a signal integrity or PDN issue emerges late, who typically decides between a die respin, package redesign, or accepting reduced performance?
• Which layers of your current stack are usually modeled last, for example die layout, interposer routing, package substrate, or PCB? Options: Die layout, Interposer routing, Package substrate, PCB/layout, All modeled together
• How often does a late package problem add more than four weeks to your program timeline? Options: Almost every project, Often, Occasionally, Rarely, Never
• What single technical or program constraint would make a co-design pilot impossible for you to run?

Constraints and readiness that determine feasibility

• If we required access to GDSII/LVS, PCB layout, and package CAD files for a four-week pilot, who must approve and how long would that approval take? Options: Security approves within 1 week, Legal approves in 2-4 weeks, Cross-org approvals in 4-8 weeks, Not possible within 8 weeks
• Do you already have a single owner or a documented process for sharing layout data across die, package, and PCB teams? Options: Yes, single owner and process, Partial, ad hoc owners, No, no central owner, We will assign if pilot approved
• List the API or file-exchange endpoints you currently use for integrations, for example EM solver export, ODB++, or IPC formats
• How mature and versioned are the layout and library files you would share for the pilot, for example strictly versioned, loosely versioned, or ad hoc snapshots? Options: Strictly versioned and tagged, Loosely versioned, Ad hoc snapshots, Not tracked
• Who on your team will be responsible for provisioning data and maintaining access during the engagement, name role and typical availability per week
• Is there any export restriction, IT security approval, or legal review that could block data sharing within six weeks? Options: No known blockers, Security review required, Legal review required, Export control constraints, Unsure

The other paths you are weighing

• Tell me about the other routes your team has proposed instead of running an external co-design pilot, for example staying sequential, buying a point SI tool, or an internal integration project
• Identify the internal teams or external vendor categories that would benefit most from keeping the current sequential flow Options: IC physical design, Package engineering, PCB/layout team, Existing EDA vendor, Foundry/OSAT
• What would have to be true about your current approach for you to decide to stay with it rather than running a pilot Options: No added schedule risk, Lower total cost than external, In-house skills can close the gap, Toolchain integration is solved, Other
• Have you estimated the effort and timeline for an internal-build option, and if so what was the rough cost or duration? Options: No internal estimate, Estimated but not formalized, Formal estimate: under 3 months, Formal estimate: 3-9 months, Formal estimate: over 9 months
• State the budget or schedule thresholds that would make an internal path preferable to an external pilot
• Name the one condition that must be true for you to reject an external pilot and stay on the current workflow

How you will measure success in the evaluation

• What would have to be proven in the evaluation for procurement and engineering to commit to a paid engagement immediately after the pilot?
• List the specific SI, PDN, and thermal KPIs you will measure during the pilot and include any target values if available
• Identify the representative designs or test vehicles you will supply, for example a high-speed serial lane, HBM stack, or chiplet interface Options: High-speed SERDES lane, DDR/HBM interface, Chiplet interposer routing, PDN-critical power island, Custom test vehicle
• Should simulated improvements fail to match hardware within your tolerance, what escalation or remediation path do you expect? Options: Joint debug session, Additional simulation runs, Hardware test vehicle, Stop pilot and reassess
• What single acceptance outcome would make you decline to proceed to deployment even if other KPIs look good

Pilot logistics and deliverables

• Could procurement place an order within two weeks if the pilot met the stated targets and acceptance gates? Options: Yes, within 2 weeks, Yes, within 2-4 weeks, No, requires longer procurement cycle, Unsure
• How many representative chip-package-board stacks will you provide for analysis during the pilot? Options: One, Two, Three or more, Not decided
• Provide the list of deliverables you require from the evaluation, for example SI reports, PDN impedance plots, thermal maps, and specific design changes
• Provide names, roles, and minimum weekly availability for the technical reviewers who will assess intermediate results
• How long should the pilot run to produce defensible SI, PDN, and thermal comparisons, for example 2, 4, or 8 weeks? Options: 2 weeks, 4 weeks, 8 weeks, Other
• State the maximum remediation budget you would commit if the pilot shows less than the targeted improvement but the approach looks promising Options: No additional budget, Under $50k, Between $50k and $200k, Over $200k, Undecided

Decision cadence and next steps

• Suppose the pilot proves the target improvements, what would accelerate you to sign the full engagement in the same week?
• Identify the stakeholders who must be briefed for procurement to issue a purchase order, including role and team
• Typically, how long do internal legal and security reviews take when onboarding a new tool partner for an evaluation Options: Less than 2 weeks, 2 to 4 weeks, 4 to 8 weeks, More than 8 weeks
• Are there program milestones or tapeout dates that create a hard stop for starting or completing the pilot Options: Yes, start window missed if delayed, Yes, completion must be before integration test, No hard stop, Unsure
• Select the communications channel you prefer during the pilot for technical questions and daily blockers Options: Shared collaboration workspace, Email thread, Weekly video calls and shared repo, Direct messaging channel
• Pinpoint the single scheduling constraint that would force you to delay or cancel the pilot

• Integrated Co-Design Review

• Confirm the current state and its cost
• You confirm the demonstrated co-design workflow would eliminate the rework and die respins you described.
• Run a co-design analysis on the buyer's representative chip-package-board stack and deliver a results summary before the follow-up session.
• Provide representative die, package, and PCB layout files along with the acceptance criteria you use for SI, PDN, and thermal sign-off.
• Define target outcomes and acceptance criteria
• You agree on measurable acceptance criteria the evaluation must meet to validate first-pass success.
• Walk through a realistic co-design scenario
• You commit to providing representative files or, if not possible, approve the seller's closest-match scenario to run the evaluation.
• Send a draft statement of work and proposed evaluation schedule for review.
• Compare results to your sequential baseline
• Validate this maps to your problem
• Agree next evaluation steps and evidence

• Integrated Co-Design Review
• Solution Experience Deck
• Solution Brief — Integrated Co-Design Review

• meeting
• slides
• document

• Unified Electromagnetic Model Assembly
• Full-Stack Signal Integrity Simulation
• PDN Co-simulation and Decoupling Optimization
• Thermal Co-simulation and Hotspot Mitigation
• Parasitic Extraction and Netlist Update
• 2.5D Interposer Floorplan and Routing
• HBM Channel Integration and Validation
• Chiplet Interface Modeling and Verification
• Bi-directional PCB–Package Data Exchange
• EM-Driven Design Rule and Stackup Generation
• Package Substrate Layout and Fabrication Outputs
• Co-Optimization Iteration Runs to Target Metrics
• Design-for-Manufacturability Corrections
• High-Frequency Interconnect Impedance Tuning

Unified Electromagnetic Model Assembly

• Provide the primary design files you will share for EM model assembly (examples: die GDS/OASIS, package substrate layout, interposer floorplan, board IPC-2581/ODB++).
• List the measured or generated S-parameter, .snp, or touchstone files you already have for die, package, interposer, and PCB interfaces.
• Which stackup document should we use to construct the unified EM stack (include layer count, dielectric constants, copper weights and thickness)? Options: Upload separate stackup documents, Provide a unified stackup spreadsheet, Supply a PDK-style stackup, Other
• Do you have a preferred EM mesh resolution or maximum frequency range for simulations (for example, up to 40 GHz or mesh cell size in microns)? Options: Yes, I will specify settings, No, request recommended defaults
• Specify who will own EM model version control and the file exchange method we should use (SFTP, platform file share, secure API endpoint). Options: SFTP, Platform file share, Secure API endpoint, Other

Full-Stack Signal Integrity Simulation

• Identify the critical nets or channels to validate and attach an example netlist excerpt (examples: DDR DQ byte lane, PCIe differential pair).
• Estimate the target eye-mask, BER, or jitter thresholds the simulation should verify against and provide numeric values or referenced spec (for example, BER 1e-12 at X UI).
• Confirm whether you require time-domain transient channel runs, frequency-domain S-parameter analysis, or both for the listed channels. Options: Time-domain, Frequency-domain, Both
• Upload the driver and receiver behavioral models you want used for channel modeling (IBIS, IBIS-AMI, or SPICE files and their versions).
• Describe any protocol-specific equalization, pre-emphasis, or de-emphasis presets that must be included in the SI model (attach parameter settings).

PDN Co-simulation and Decoupling Optimization

• Identify the target PDN impedance profile or budget across frequency that we should design to (for example, target Z < X mOhm from 10 kHz to 100 MHz).
• List the on-board and on-package decoupling capacitors available for optimization including values, package types, and placement constraints.
• Estimate which power rails and VRM output models (attach SPICE/behavioral models) must be included in the co-simulation.
• Do you have transient current waveforms or per-mode power maps to drive PDN simulations (attach CSV power map if available)? Options: Yes, will attach power maps, No, please use representative waveforms
• Specify the PDN acceptance thresholds for this scope (for example, maximum voltage droop of X mV under a Y A transient and target impedance not to exceed Z mOhm at specified frequency bands).

Thermal Co-simulation and Hotspot Mitigation

• Provide the power dissipation map per die region or component in watts and indicate steady-state versus peak conditions for thermal simulation inputs.
• Estimate the ambient and boundary conditions we should assume (examples: 25°C still-air, forced convection at specified CFM, or thermal chamber profile).
• Identify the thermal interface materials and their thermal conductivity values used in your stack (TIM part numbers or conductivity in W/mK).
• Do you require transient thermal runs for pulsed workloads or steady-state only for hotspot analysis? Options: Transient and steady-state, Steady-state only, Transient only
• Specify the maximum allowable hotspot temperature or junction-to-case delta that will be used to judge thermal mitigation success (for example, Tj < 125°C or ΔTcase < 10°C).

Parasitic Extraction and Netlist Update

• Attach the current extracted parasitic files you have (examples: .elp, .snp, .sp, or extraction reports) and note the tool settings used to generate them.
• Which netlist format must be updated for downstream simulation and which simulator will consume it (SPICE, IBIS, Verilog-AMS, other)? Options: SPICE, IBIS, Verilog-AMS, Other
• Specify the extraction granularity required: per-pin RLC, per-segment, or lumped RLC between nodes, and give an example net where this granularity matters. Options: Per-pin RLC, Per-segment, Lumped between nodes, Other
• Confirm the net naming convention and net mapping file we should use to reconcile die, package, and board nets during the netlist update process.
• Who will sign off on updated netlists as ready for simulation handoff and what evidence (for example, a verified TD/FD run, regression plots, or sign-off checklist) will they require?

2.5D Interposer Floorplan and Routing

• Provide the interposer PDK or substrate guidelines including layer counts, allowable via types, and maximum via aspect ratios.
• List die placements, microbump pitch, and the floorplan PDF you will supply for interposer routing studies.
• Which routing density zones or likely congestion regions should we prioritize in the routing feasibility analysis?
• Are there keep-out zones or OSAT manufacturing constraints we must enforce on the interposer (attach constraint doc if available)? Options: Yes, will provide constraints, No keep-outs
• Specify any timing or latency constraints across interposer routes that must be validated (for example, max delay between chiplet A pin X and B pin Y).

HBM Channel Integration and Validation

• List the HBM stack configuration (layers per stack, microbump pitch) and the number of HBM channels to be validated.
• Provide available HBM PHY test vectors or datasets for functional channel validation or indicate if you need representative vectors supplied. Options: Yes, will provide vectors, No, request representative vectors
• Which JEDEC HBM revision or spec should be referenced for timing, signal amplitude, and ordering constraints during validation?
• Do you require thermal coupling between HBM stacks and die in the co-simulation runs (for example, stacked HBM thermal conduction to package lid)? Options: Yes, No
• Identify the DQ and CA grouping and the routing topology used (T-branch, fly-by, point-to-point) that must be modeled for channel performance.

Chiplet Interface Modeling and Verification

• Describe the chiplet interconnect standard and pinout mapping to model (for example, C2C-style lane mapping or custom LVDS groups).
• Which timing constraints at the die I/O boundary must be preserved during co-optimization (examples: setup/hold margins in ps)?
• Provide required crosstalk or isolation thresholds between adjacent chiplet channels in dB that the model must meet.
• Are on-chip termination schemes fixed or can they be tuned during co-design; attach any related configuration docs. Options: Fixed, Tunable, Unknown
• Specify the functional verification testbench or behavioral model used for chiplet-level verification and indicate file format for exchange.

Bi-directional PCB–Package Data Exchange

• Which PCB and package file formats will you supply for bi-directional exchange (examples: IPC-2581, ODB++, Gerber plus netlist)? Options: IPC-2581, ODB++, Gerber + Netlist, Other
• List the netlist and attribute fields that must be preserved during exchange (pad names, net classes, impedance targets, pin mappings).
• Do you require automated reconciliation of copper geometry changes between package and PCB layouts during the exchange workflow? Options: Yes, No
• Specify the synchronization cadence and ownership rules for file syncs (for example, weekly snapshot, per-iteration handoff and who pushes updates).
• Who in your team will be the integration point for resolving package/PCB mismatches and how should they be contacted (role and contact method)?

EM-Driven Design Rule and Stackup Generation

• Which manufacturing design rules arising from EM findings must be encoded (examples: minimum trace width, spacing, plane splits) and where are they documented?
• Provide the target impedance control tolerances per channel type you require for generated stackups (for example, 100 ohm ±10%).
• Do you need exportable DRC or rule files for your PCB/package layout tool and which rule file format is required for vendor import? Options: IPC-2581 rule set, DRC script, Other
• Specify whether thermal via stitching or cutouts are allowed in signal layers according to your fabricator and provide constraint examples if restricted. Options: Allowed, Restricted with constraints, Not allowed
• Identify any high-frequency shielding, guard traces, or split-plane requirements that must be enforced when generating stackups.

Package Substrate Layout and Fabrication Outputs

• Provide the package substrate release format you require and the BOM level needed for fabrication outputs (for example, fabricator-ready Gerber + fabrication notes).
• Which specific fabrication deliverables do you need for the substrate vendor (Gerber, drill files, pick-and-place, BOM, fabrication notes)? Options: Gerber + Drill, Pick-and-place + BOM, Fabrication notes only, All of the above
• Do you require fabrication-ready panelization and aperture details tailored to a named fabrication house or generic outputs are acceptable? Options: Tailored to a fabricator (we will provide), Generic outputs sufficient
• Specify required material data for the substrate (core dielectric constants, prepreg types) and acceptable supplier tolerances.
• Who on your team will approve fabrication outputs and which document constitutes formal sign-off (for example, a signed fabrication release checklist)?

Co-Optimization Iteration Runs to Target Metrics

• List the electrical and thermal target metrics we must reach through co-optimization iterations (examples: eye height in mV, BER threshold, PDN droop in mV, hotspot temp in °C).
• Which iterations are included in the fixed-fee scope and which will be treated as change orders per the statement of work (for example, up to 3 iterations included)? Options: Up to 3 iterations included, Custom per SOW, Time-and-materials beyond initial
• Specify the expected cadence and maximum number of co-optimization runs you anticipate during the engagement (examples: weekly cadence up to 6 runs, milestone-driven). Options: Weekly cadence, up to 6 runs, Per milestone cadence, variable, Other
• Provide the measurement methods and baseline datasets we will use to evaluate iteration improvements (examples: TDR captures, VNA S-parameters, thermal chamber profiles).
• Who will coordinate and approve each iteration handoff on your side and what turnaround time do you expect for feedback (for example, 5 business days)?

• current_state
• stakeholders
• gaps
• success_criteria
• desired_state
• decision_readiness
• current_state
• decision_readiness
• desired_state
• success_criteria
• gaps
• stakeholders
• stakeholders
• decision_readiness
• current_state
• decision_readiness
• decision_readiness
• decision_readiness
• decision_readiness

• Non-Disclosure Agreement (NDA)
• Master Services Agreement (MSA)
• Statement of Work (SOW)
• Subscription Agreement / Order Form
• Data Processing Agreement (DPA)
• Data Access Authorization
• Acceptance Criteria & Deployment Gates
• Intellectual Property & Results Licensing Addendum
• Change Order Agreement
• Invoicing and Payment Schedule
• Export Control & Security Addendum (conditional)

• Go-live health check (weeks 1-4)
• First measurement review (weeks 4-10)
• Acceptance gate review (around day 90)
• Quarterly outcomes and issue backlog review
• Annual lessons learned and enhancement roadmap

• Update the shared issue tracker with current status, priority, and new target resolution dates for critical items.
• If any criterion failed, agree remediation tasks with target completion dates to achieve final acceptance.
• Confirm the incumbent tool/process decommissioning or read-only retention and archive timeline to prevent dual-system usage.
• Publish the acceptance decision and supporting evidence package into the shared project workspace.
• Document the remediation plan for any failed criteria, including specific analysis runs, design changes, and validation checkpoints.
• Complete incumbent data archive or read-only retention and provide confirmation of archive completeness in the shared workspace.
• Trend review of key metrics
• Confirm whether the primary SI and PDN metrics remain within acceptable bounds and identify any upward trends in incident count.
• Prioritize the defect and enhancement backlog and agree near-term resolution targets.
• Agree any lightweight process or configuration adjustments needed to reduce recurring incidents.
• Reconfirm deployment completion and acceptance criteria owners
• Publish a prioritized enhancement request list with rough effort estimates and proposed schedule windows.
• Record any measurement or process adjustments and schedule a verification run to confirm the change reduced noise or false positives.
• Year-to-date outcome summary versus scope
• Produce a documented lessons learned record and proposed process changes to reduce future rework risk.
• Agree a prioritized enhancement roadmap for the next 12 months and the operating SLA for the shared issue/enhancement channel.
• Confirm archival of final artifacts and the authoritative location for reference models and test datasets.
• Publish the lessons learned document and recommended process changes to the shared workspace.
• Establish and maintain the shared issue and enhancement channel with documented response and resolution SLAs.
• Archive final validated models, representative design files, and measurement datasets in the agreed storage location and confirm accessibility.
• Confirm the deployment completed to the agreed configuration and all access requirements are met.
• Document and schedule remediation for any high-priority defects preventing expected use.
• Confirm the shared issue channel and timing for the first measurement review.
• Publish a deployment verification report listing completed checks, outstanding defects, and temporary workarounds.
• Provide an export of current user access and training completion status for review.
• Create the shared issue tracker channel and seed it with the initial defect list and target resolution dates.
• Measurement scope and data sources
• Establish whether signal integrity margin and PDN impedance are trending toward Solution Scope targets and identify gaps.
• Agree a short list of corrective actions with completion dates to move metrics to the acceptance gate.
• Confirm the evidence package and data owners for the acceptance gate meeting.
• Execute the agreed additional SI/PDN/thermal analysis runs on the representative stack and deliver updated result files.
• Publish the measurement dataset and analysis methodology used for metric calculation to the shared workspace.
• Log any changes to representative designs or test vectors and the reason for each change.
• Restate acceptance criteria and evidence requirements
• Produce a documented acceptance decision against each numeric criterion recorded in Solution Scope, with evidence from Solution Evaluation.
• Open issue and defect backlog review
• Capture lessons learned and process improvements
• Present outcome data against each acceptance criterion
• Present measured outcomes versus baseline and targets
• Deployment and integration verification
• Enhancement requests triage and scheduling
• Document pass or fail per criterion and formal acceptance decision
• Enhancement roadmap and maintenance channel
• Diagnose gaps and root-cause analysis
• User access and onboarding status
• Operational refinements and process updates
• Close-out tasks and archival
• Early adoption signals and anomalies
• Remediation plan for any failed criteria
• Agree corrective actions and timeline to acceptance gate
• Incumbent wind-down and data migration confirmation
• Open issues and immediate remediation plan
• Confirm readiness for the acceptance gate review
• Agree next checkpoint and communication channel