Quick baseline: timeline and essential counts

• What's your target tapeout window? Options: Within 2 weeks, 2-4 weeks, 4-8 weeks, More than 8 weeks, Unsure
• What's the current count of open DRC violations in the primary database you expect us to assess? Options: Fewer than 100, 100-500, 500-2,000, More than 2,000, I need to confirm
• How many timing paths are currently flagged as unresolved or at risk in your latest STA reports? Options: None, Fewer than 100, 100-1,000, More than 1,000, Unknown
• Who will be the main technical contact we work with day to day, and what is their role title? Options: Design Director, Tapeout Engineer, Senior Physical Designer, Program Manager, Other
• Walk me through the last time your team faced a foundry rejection, what slipped past review, and what the root cause was
• When do you expect an upstream freeze for netlist or ECOs relative to the tapeout date? Options: No freeze planned, Within 1 week, 1-2 weeks, 2-4 weeks, Frozen now

If the first submission fails, here is what breaks

• If the foundry rejects your first mask data submission, what is the immediate schedule and financial impact you anticipate?
• Estimate the likely mask respin or recovery cost you would face from a failed first submission Options: Less than $50k, $50k to $150k, $150k to $300k, More than $300k, Unknown
• Which downstream milestones would slip if you missed the tapeout date? Options: Manufacturing start, Customer demo or delivery, Revenue recognition, Tool reservations or bookings, Certifications or compliance, Other
• How much contingency time exists between a potential respin and critical customer commitments? Options: None, Less than 1 week, 1-2 weeks, More than 2 weeks, Unknown
• Which stakeholder would apply the most pressure to recover schedule after a rejection? Options: VP Engineering, Program Manager, Product Owner, Foundry Liaison, Manufacturing Lead, Other
• What single consequence of a failed first submission would make you cancel or delay the project entirely?

Where the database feels fragile today

• Which parts of your layout feel most likely to trigger an unexpected foundry rejection? Options: Full-chip density/fill areas, Certain IP blocks, Antenna-sensitive metal stacks, Via or via-chain regions, Power/ground grid areas, Other
• Are there legacy IP blocks or third-party macros lacking verified PDK support or clear owners? Options: Yes, multiple blocks, Yes, one block, No, all covered, Unsure
• Which process-rule categories currently generate the highest volume of violations in your reports? Options: Metal density and fill, Antenna rules, Geometry spacing rules, Via redundancy and stacking, Well/tap rules, Power grid violations, Other
• How long would it take your internal team to remediate the existing DRC backlog at current headcount and pace? Options: Less than 1 week, 1-2 weeks, 2-4 weeks, More than 4 weeks, Cannot estimate
• Tell us about any IP or blocks with limited access, special signoff steps, or escrow requirements
• Is there any IP or block with missing source files or no available owner that would prevent completing remediation in your timeline? Options: Yes, blocks without owners, Yes, missing source files, No, Unsure

Alternatives on the table

• Which option are you most likely to choose instead of engaging an external tapeout readiness partner? Options: Keep it internal with existing team, Use current incumbent vendor, Hire short-term contractors, Delay tapeout, Other
• Which internal resources would be reallocated if you pursued the work in-house? Options: Physical signoff engineers, RTL or block owners, Contractors, No one available, Other
• If you stayed with the current approach, what specific condition would have to be true to avoid a mask respin?
• Has anyone on the team proposed solving this without an outside vendor or partner? Options: Yes, suggested internal effort, Yes, suggested incumbent vendor, No proposal yet, Unsure
• Which proof point would make you select an external partner today instead of the alternatives? Options: Foundry acceptance references at same node, Signed SLA for first-pass acceptance, Embedded project manager within 72 hours, Fixed-price remediation option, Daily live dashboard access, Other
• What condition would let you commit to a partner in the next 72 hours?

Clear definition of success for submission

• Which foundry acceptance checks must pass on the first submission for you to call it successful? Options: DRC pass for critical layers, Timing meeting your release signoff target, Density and fill compliance, Antenna rule pass, Reticle layout and array checks, Mask data format and layer mapping, Submission paperwork and authorizations, Other
• Who at your side must sign off before we hand off to the foundry, and what is their role title? Options: Design Director, Tapeout Engineer, QA Lead, VP Engineering, Foundry Liaison, Other
• Describe your current approach to prioritizing violations by acceptance risk and schedule impact
• Which daily KPI on a live dashboard would best reassure your VP of Engineering? Options: Open DRC count, Critical timing paths at risk, Fill coverage percentage, Critical block signoffs, Estimated days to foundry acceptance, Other
• If our assessment showed more than 25 percent of critical violations required design changes, would you still proceed to meet your tapeout date? Options: Yes, accept risk and proceed, Delay tapeout, Proceed with targeted design fixes, Unsure

Can we actually run the plan, practical constraints

• Which of these prerequisites are currently missing that would block starting remediation within three business days? Options: Database access with full permissions, Foundry PDKs and rule decks, Signed NDAs and approved data transfer, Tool licenses matching signoff environment, Dedicated tapeout engineer on your side, Submission window reserved with foundry, Other
• Are there compliance, security, or legal approvals required before we can access your design data? Options: Yes, formal security review, Yes, legal approval needed, No approvals required, Unsure
• Which EDA tool versions are used for final signoff and are any of them unsupported or missing licenses? Options: All standard signoff versions available, Some versions unsupported or missing licenses, We use custom or older tooling, Unknown
• Name the team or role that controls the accounts and can grant integration credentials Options: IT or Security, Design Ops, Tooling Team, Program Manager, Other
• How many engineers from your side can participate in daily triage and verification during execution? Options: 0, 1, 2-3, 4-6, More than 6
• Is there any contractual clause, export control, or third-party restriction that would prevent us from exchanging mask data with the foundry on your behalf? Options: Yes, No, Unsure

Team rhythm, escalation, and integration

• What level of daily integration with your engineers can we expect for the next six weeks? Options: Full daily embedded collaboration, Daily sync with a designated lead, Three times a week, Weekly, As needed only
• Please name the role that will hold final signoff authority and describe their decision criteria
• Which communication channels should we use for daily triage and urgent escalation? Options: Slack or equivalent, Email, Ticketing system, Daily standup calls, Other
• How quickly can your team review and approve a remediation patch once we deliver it? Options: Within a few hours, Same day, 24-48 hours, More than 48 hours, Depends on scope
• Tell us your preferred cadence and level of detail for dashboard updates so the VP gets the right visibility
• If our engineers need continuous access to your database for 72 hours before a formal SOW is signed, would you authorize that under your security controls? Options: Yes, Yes with additional security controls, No, Need executive approval

Pressure test the schedule

• What upstream freeze point must hold for a realistic chance of first-pass acceptance by your target tapeout date? Options: No freeze imposed, 3 weeks before tapeout, 2 weeks before tapeout, 1 week before tapeout, Frozen now
• Which calendar events or customer commitments lock the tapeout date for you? Options: Customer demo or shipment, Manufacturing slot, Investor or public milestone, Compliance deadline, Sales launch, Other
• If post-freeze changes are unavoidable, how will scope and priority be decided and who signs that decision?
• How flexible is your mask shop booking if we need to shift by one week? Options: Fully flexible, One week lead time required, Non-negotiable, Unknown
• Estimate the contingency budget you have for an unexpected respin or accepted delay Options: None allocated, Less than $100k, $100k to $300k, More than $300k, Undisclosed
• If our assessment recommends delaying tapeout to avoid a high-risk submission, who can authorize that decision and how quickly must it be made?

Decision levers and next steps

• What is the one thing we must deliver in the assessment to get you to sign a remediation SOW within a week?
• What internal approvals are required to sign a SOW and how long do they typically take? Options: Single executive approval, Procurement and legal review, Legal only, Multiple stakeholder approvals, Unknown
• What references or evidence would convince your VP of Engineering to proceed now? Options: Foundry acceptance references at same node, Case studies with similar design size, Engineer resumes with tapeout counts, Live dashboard sample, Other
• If we deliver an initial prioritized closure plan within 72 hours, who needs to see it and what decision will they be asked to make?
• Select your target signature timeline for the SOW if terms and scope match expectations Options: Within 24 hours, Within 72 hours, Within 1 week, Longer than 1 week, Unsure
• If everything aligns, are you authorized to approve a start date immediately, or would you need to escalate? Options: Authorized to approve start date, Need executive sign-off, Need procurement or legal process, Not authorized

• Technical Walkthrough and Integration Plan

• Confirm the current state and its cost
• You confirm the remediation approach eliminates the rework and mask-respin risk you described.
• Deliver a tailored remediation roadmap with prioritized violation closure plan and estimated closure timelines within 48 hours.
• You confirm the integration plan will run in your EDA environment within the first week given the listed access and tool versions.
• Walk through the remediation approach for representative violations
• Provide read/write access to the current design database, a list of EDA tool versions and license access, and any foundry acceptance appendices within 24 hours.
• Show the EDA integration plan and sample run
• You agree on the minimal evidence set required to approve submission, for example a signed acceptance checklist and specific verification reports.
• Produce a draft acceptance checklist mapping foundry criteria to verification outputs for the next review meeting.
• Map acceptance criteria to the closure checklist
• Validate that this matches your needs

• Technical Walkthrough and Integration Plan
• Technical Walkthrough Deck
• Technical Walkthrough Solution Brief

• meeting
• slides
• document

• Non-Disclosure Agreement (NDA)
• Master Services Agreement (MSA)
• Statement of Work (SOW)
• Data Access & Authorization
• Data Processing Agreement (DPA)
• Engagement Retainer & Payment Schedule
• Service Level Agreement (SLA) & Dashboard KPIs
• Change Order Agreement
• Intellectual Property & Deliverables License
• Foundry Submission Authorization
• Termination & Refund Terms
• Industry Compliance Addendum (conditional)

• desired_state
• success_criteria
• current_state
• gaps
• decision_readiness
• stakeholders
• success_criteria
• stakeholders
• decision_readiness
• desired_state
• current_state
• gaps
• gaps
• current_state
• desired_state
• success_criteria
• stakeholders
• decision_readiness
• decision_readiness
• decision_readiness
• decision_readiness
• decision_readiness

• Run and Close DRC Violations
• Perform LVS and Schematic Corrections
• Insert and Verify Fill Patterns
• Antenna Rule Repairs
• Implement Via Redundancy and Hardening
• Apply Metal Density and Gradient Corrections
• Timing ECOs and Critical-Path Fixes
• Parasitic Extraction and Netlist Update
• Mask Data Preparation and Reticle Layout
• GDSII/OASIS Streamout and Conversion
• Assemble Foundry Submission Package
• Execute Foundry Acceptance Test Runs
• Deploy Real-Time Violation-Tracking Dashboard

Run and Close DRC Violations

• Which DRC rule deck format does your process design kit (PDK) supply for this design (example: SVRF-equivalent, Tcl rule script, proprietary format)? Options: Standard PDK rule deck (SVRF-equivalent), Custom in-house DRC scripts, Third-party rule deck, Unknown / need assistance identifying
• Who on your team is the authorized owner for DRC closure decisions and who is the technical contact for DRC run access?
• How many open DRC violations exist today, broken down by severity (Class A / Class B / Class C)? Options: Provide counts for each severity (free text), Unknown — run required to quantify
• List the DRC run artifacts you can provide immediately (DRC report filenames, full run logs, baseline deck hash, last-run timestamps).
• Provide the preferred turnaround SLA per DRC class for remediation tasks during the tapeout window Options: Same day (8 hours), 24-48 hours, 3-5 business days, Custom SLA — specify
• Confirm the maximum number of full-chip DRC iterations included in scope before out-of-scope fees apply Options: 1 full streamout, 2 full iterations, 3 full iterations, Unlimited (time-and-materials)

Perform LVS and Schematic Corrections

• Specify the golden netlist format you will supply for LVS comparison (extracted SPICE, LEF/DEF mapped netlist, harmonized gate-level netlist) Options: Extracted SPICE (SPEF/SLPF available), Gate-level netlist (Verilog/VHDL), LEF/DEF mapped netlist, No golden netlist — require extraction service
• Indicate which LVS report artifacts you can share (LVS summary, mismatch list with coordinates, connectivity deltas) Options: Full LVS report, Mismatch list with coordinates, Netlist diff only, None available yet
• Estimate the share of IP blocks that already have LVS-clean golden netlists versus those needing extraction or fixes Options: All blocks LVS-clean, Most (70%-99%), Some (25%-69%), Few (<25%)
• Identify any specific analog, mixed-signal, or foundry-certified IP blocks that historically trigger LVS mismatches (provide block names/IDs)
• Select your preferred discrepancy handling policy for LVS failures Options: Automatic net-aliasing and documented fix, Root-cause analysis and manual correction only, Escalate each LVS error to block owner for decision
• When is the most recent gate-level netlist capture (date) and does it align with the current layout version you will submit? Options: Same revision — aligned, Different — minor revisions, Different — major revision (requires reconciliation), Unknown

Insert and Verify Fill Patterns

• List the fill-pattern libraries or fill-rule recipes your PDK expects (library filenames or catalog identifiers)
• Provide the expected metal density target ranges and window sizes from your foundry checklist (e.g., 30%-70% over 20um window)
• Confirm whether fill insertion should preserve antenna mitigation and special keepout regions (procedural constraint) Options: Preserve antenna mitigation and keepouts, Apply fill without antenna considerations, Need consultation on keepouts
• Specify the maximum permitted pattern adjacency or minimum spacing constraints the fill engine must respect (attach rule excerpts if available)
• Indicate any known blocks where servo or embedded test patterns require manual exemption from automated fill
• Estimate hours required to insert and verify full-chip fill patterns given your current design size (provide best guess or range) Options: <40 hours, 40-120 hours, 120-240 hours, >240 hours

Antenna Rule Repairs

• Identify the antenna rules from your foundry checklist that are applicable (example artifacts: antenna ratio thresholds, cumulative metal rules)
• Which nets or macros historically show antenna violations in this design (provide net names or block IDs)?
• Provide the antenna report outputs you can supply (violation list with coordinates, offending path traces, antenna ratio values) Options: Full antenna report with coordinates, List of nets only, No report available yet
• Confirm your preferred repair strategy for antenna violations Options: Insert diodes or antenna fix cells, Local routing changes, Net re-driver placement, Escalate to design owner for approval
• Outline any supply-chain or IP licensing constraints that prevent insertion of library fix cells into certain blocks
• Estimate the maximum allowed timing impact for antenna fixes on critical nets (ps slack or % of path delay) Options: No impact allowed (<1% delay), Small impact allowed (1-5% delay), Moderate allowed (5-10% delay), Significant allowed — need review

Implement Via Redundancy and Hardening

• Specify the via redundancy rules required by the foundry (for example: minimum 2x redundant vias on Mx to My transitions)
• Indicate which layer transitions in your design are most sensitive and require manual review for via hardening
• Identify any restricted layout areas or legacy IP blocks where via geometry cannot be modified
• Select the scope for automated via hardening we should run Options: Full-chip automated hardening with verification, Targeted hardening on critical nets only, Manual changes only upon escalation
• Provide the via design-rule excerpts or PDK notes that define acceptable redundancy and minimum enclosure values
• Estimate the effort (person-hours) to apply and verify via redundancy across the full chip Options: <40 hours, 40-120 hours, 120-240 hours, >240 hours

Apply Metal Density and Gradient Corrections

• Where are the canonical metal density maps and prior density reports for this design stored (path or URL)?
• When was the last metal density analysis run and what windows and layer sets were used?
• Specify the foundry density constraints and gradient rules we must satisfy (include numeric thresholds and window sizes)
• Indicate any custom density rules applied to memory arrays, analog macros, or cut layers that differ from standard density windows
• Choose the remediation tolerance for density corrections (how aggressively we insert/trim patterns) Options: Conservative (min change), Balanced (target foundry ranges), Aggressive (maximize compliance)
• Estimate how many density violation hotspots are present and the maximum size of contiguous hotspots (in microns or estimated tile count)

Timing ECOs and Critical-Path Fixes

• List the latest static timing analysis (STA) reports you can provide (timing summary, failing path list, SDC used)
• Specify the STA tool version and the timing constraints (SDC filename) used for the last signoff run
• Identify the top critical paths by name or endpoint nets that require ECO attention
• Indicate whether we have authority to apply register re-timing, buffer insertion, or net-tie changes for timing fixes Options: Full ECO authority, Only non-invasive changes, Require design owner approval per fix
• Estimate acceptable timing slack thresholds for ECOs to be considered successful (e.g., >0 ps, >100 ps margin) Options: Must meet zero slack or better, Require X ps positive margin — specify in free text, Design owner will define per path
• Provide the regression plan and test vectors you expect us to run after ECOs to validate timing (unit tests, gate-level sims, etc.)

Parasitic Extraction and Netlist Update

• List the parasitic extraction formats you require for netlist update (SPEF, RSPF, DSPF) and which one the foundry prefers Options: SPEF, RSPF, DSPF, Other/unspecified
• Provide the target corners and PVT (process-voltage-temperature) corners for parasitic extraction runs
• Identify which extracted netlist artifacts must be regenerated (timing-aware netlist, LVS-clean netlist, parasitic-annotated SPICE)
• Indicate any netlist name-mangling or port mapping rules required to keep post-extraction netlist compatible with your regression flow
• Estimate the expected size (bytes or nodes) of extracted parasitic files for the full chip to size tool resource planning Options: <10GB, 10-50GB, 50-200GB, >200GB
• Identify any special ground-signal or substrate net handling rules to apply during extraction

Mask Data Preparation and Reticle Layout

• Specify the reticle layout parameters you require (reticle tile size, die-packing orientation, frame margins)
• Provide the mask-layer mapping for your foundry submission (layer-to-mask map or mapping file)
• Identify whether the design requires multi-die reticle assembly, stitched reticles, or special write-field shot planning Options: Single-die reticle, Multi-die reticle / array, Stitched reticle, Unknown — need consultation
• Indicate any guardbanding or OPC (optical proximity correction) handoff artifacts the foundry expects with the reticle
• Estimate the time window and blackout dates for final reticle layout approval before submission
• Identify primary constraints for write-field alignment and reticle notch orientation that must be preserved

GDSII/OASIS Streamout and Conversion

• Where are the canonical layout files stored and in which format do you currently keep them (GDSII, OASIS)? Options: GDSII, OASIS, Both available, Other / custom
• When was the last successful streamout and do you have a validated streamout script or recipe (include script name/path)
• Specify the layer map and any layer remapping rules we must apply during conversion for foundry submission
• Indicate whether compression options, checksum requirements, or tombstone metadata are required for the foundry's OASIS/GDS package
• Provide the maximum allowed streamout file size constraints and whether streaming across multiple files is acceptable Options: Single file required, Multi-file permitted, Prefer compressed multi-file
• Identify any post-streamout verification steps you require (layer count check, polygon parity, checksum) and expected pass thresholds

• Go-live health check (weeks 1-4)
• First measurement review (weeks 4-10)
• 90-day realization and lessons learned
• Quarterly post-tapeout operational review

• Schedule the next quarterly review and distribute the pre-read metrics package one week in advance.
• Confirm first-pass acceptance outcome
• Confirm the first-pass acceptance status as recorded in Foundry Acceptance Checklist and surface any outstanding acceptance conditions.
• Reduce the number of open post-submission foundry issues and define target MTTR improvements where applicable.
• Produce a documented lessons-learned summary and an operational procedure for handling enhancement requests.
• Publish the lessons-learned document and circulate it to the design and process teams for archival.
• Open enhancement requests in the shared backlog and tag each with expected impact on post-submission issue count or MTTR.
• Activate the agreed post-tapeout communication channel and document triage rules and escalation steps in the channel's pinned notes.
• Trend review, issues and MTTR
• Ensure monthly post-tapeout issue count and MTTR are stable or improving toward targets recorded in Remediation Scope.
• Select the top enhancement requests for execution in the coming quarter and document expected impact.
• Confirm there are no unresolved operational risks that would jeopardize future tapeouts.
• Produce a prioritized enhancement plan for the next quarter with expected impact on issue count or MTTR.
• Close any low-value legacy items that remain in the backlog and archive their rationale.
• Re-confirm success criteria and owners
• Confirm all deployment checklist items are complete and owners for each acceptance criterion are named.
• Identify and log any critical blockers that would prevent reliable post-tapeout monitoring.
• Agree short-term actions to resolve critical blockers within an agreed window.
• Publish deployment verification checklist and confirm dashboard access for the buyer's team.
• Create an itemized blocker list with target resolution dates for any critical issues found in this session.
• Enable the shared post-tapeout communication channel and distribute escalation contacts.
• Present first-measurement data
• Determine whether number of open DRC violations at submission and violation closure rate are meeting targets recorded in Remediation Scope.
• Identify root causes for each off-track metric and agree a time-bound remediation plan.
• Commit to dashboard and alert updates to provide earlier detection of metric regressions.
• Publish a prioritized remediation task list linking each task to the metric it affects and target resolution dates.
• Configure automated alerts for metric regressions and confirm recipients for each alert channel.
• Schedule a follow-up status checkpoint to validate progress against the agreed timeline.
• Deployment and access verification
• Compare results to targets in Remediation Scope
• Review post-submission issue inventory and MTTR
• Enhancement backlog prioritization
• Capture lessons learned and process changes
• Early signals and dashboard sanity check
• Open remediation and operational risk review
• Root-cause diagnosis for gaps
• Agree post-tapeout support channel and enhancement backlog workflow
• Short actions and next steps
• Open blockers and immediate risks
• Agree corrective actions and timeline
• Agree immediate remediation actions
• Update monitoring and alert thresholds